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Advanced Packaging Conference (APC)

Enabling Heterogeneous Integration in Package for New Applications

Digitalization is already changing most areas of our life in this the third decade of the 21st century. It will continue to impact the way we live, work, communicate, cooperate, acquire, process, store data and exchange information. This affects all markets using applications and solutions enabled by electronics, such as industrial, automotive wireless communication, medical, data processing and storage, cloud, fog and edge computing. IoT/IoE (Internet of Things/ Internet of Everything), deep machine learning, AI (Artificial Intelligence), AR/VR (Augmented Reality/ Virtual Reality), Autonomous driving, Industry 4.0 and other key trends are entering into more and more areas of our life, making it easier, more efficient and safe.

Electronics Packaging and Test, particularly of ICs (Integrated Circuits), Sensors and MEMS (Micro-Electro-Mechanical Systems, MOEMS (Micro-Optoelectronic Mechanical Systems) and Photonic devices, manufactured using latest technologies, is gaining further importance as an integrated part of the system solutions required to adequately serve those trends. The package is becoming a functional part of electronic systems with significant impact on their performance, form-factor and cost. Miniaturization and an increasing level of integration at packaging level targets more functionality in less space, which is promising higher system performance, smaller system size and lower system cost. The way to achieve all of this is Heterogeneous Integration (HI) of multiple bare dies with different functionality from different manufacturers.  Chiplets and interposers, already packaged components like MEMS and MOEMS, discrete passives and IPDs (Integrated Passive Devices) can all be combined in SiP (System-in-Package). This requires a system approach with Chip-Package-Board co-design and co-development with a close cooperation along the complete semiconductor supply chain.

New advanced packaging solutions can’t be developed in isolation. They require manufacturing equipment with advanced capabilities processing new functional materials with manufacturing process IP developed in-house or provided by third parties. EDA (Electronic Design Automation) and Simulation tools and methods need to be enhanced for SiP, and Chip-Package-Board co-design. ADK (Assembly Design Kits) need to be developed and linked to PDK (Process Design Kits) of chip design and wafer manufacturing technologies. Design for reliability and design for test is required. The importance of electro-magnetic performance, thermal and thermo-mechanical simulation on package level, ideally a complete virtual prototyping, is increasing, shortening development time and reducing cost significantly. To ensure success, a collaborative approach with new ideas, close co-operations, alliances, partnerships and new business models along the semiconductor supply chain is required.

At this year’s APC, we want to present advances and latest developments in this field. If your company is part of the semiconductor supply chain, and you are contributing with innovations, new developments, concepts, partnership and business models to enable Heterogeneous Integration in Package for new Applications, you are invited to submit an abstract.

Submitted papers should cover; Packaging/ Assembly and Wafer/ Package Test innovation and new developments in Design, EDA, ADK, Simulation, Manufacturing Equipment and Material and Process IP, which support the enabling of Heterogeneous Integration in Package for new applications.  We encourage participation from companies and individuals that can demonstrate advancements in the following areas:


Packaging/Assembly:

  • Advanced Packaging and Interconnect Technologies
  • Heterogeneous Integration in advanced densely packed System-in-Package
  • Multiple die, Chiplets, Interposer, MEMS and Sensor Integration
  • Optoelectronics, MOEMS and Photonics Packaging and Integration in SiP
  • High Voltage and Power Packaging
  • Chip Embedding Packaging Technologies
  • Wafer-Level Packaging (Fan-In and Fan-Out)
  • Scaling from Wafer to Panel Level Packaging
  • System-in-Package
  • Chip-Package-Interaction (CPI) and Reliability
  • Modelling, Simulation, Virtual Prototyping
  • New Functional Packaging Materials for Higher Reliability and Yield
  • Characterization methods for reliable materials data as input for the simulations
  • Non-destructive test methods for quality control and failure analysis of packages
  • Additive Assembly technology
  • Thin Wafer/ Panel Handling
  • Process IP Development and Process Control
  • Quality and Reliability Assurance
  • Metrology and Inspection Methods
  • Failure Modes and Analysis
  • Cost Reduction of Advanced Packaging
  • Markets and Applications

Wafer/Package Test:

  • SiP Test Concepts (partially and fully assembled)
  • BIST (Built-In Self-Test), redundancy and repair
  • Test of High Frequency Applications e.g. 5G
  • Wafer-Level Package Handling and Test
  • Probing and alignment for Small Contact Pitches
  • Overcoming Packaging Limits to enable test at high parallelism
  • Packaging and Test: Strategies for High-energy Alpha Wave Sensitive Materials
  • Validation of Interconnects at multiple temperatures (room, hot and cold)
  • Contactless Testing;
  • Validation of Interconnects at High Power (high voltage and/or current)
  • Validation of Interconnects at Microwave Frequencies
  • Test Strategies for Multi-Chip Packages
  • Testing Packages with Integrated Sensors
  • Using Big Data Analytics from Test to Optimize Packaging Process
  • Using Simulation to optimize Test Interconnect Solutions

General guidelines - The abstract submission deadline has expired. We thank all authors who have submitted their abstracts. 

  • Please submit your abstract, biography and a photo through our link by Wednesday 10 June 2020. Abstracts submitted via other methods will generally not be accepted.
  • The conference language is English.
  • The abstract should have between 250 and 500 words (Starting with descriptive paragraph identifying issue addressed and solution). Please focus on the news instead of describing state-of-the-art.
  • Abstract modifications, changes and corrections will be accepted until 10 June 2020.
  • Selected presenters will be notified in June 2020.


Your presentation may not be included in the review process unless the information is complete. Evaluation criteria include significance, usefulness for the manufacturing world and clarity and accuracy as a paper. Abstracts will be peer-reviewed and selected relative to the points above. We encourage application related presentations, i.e. on joint projects between users and suppliers. Papers are to be non-commercial and focus on the technical/economical merits of a process rather than the individual company’s product benefits.

 

SEMI Europe Advanced Packaging Conference (APC) Committee:

  • Steffen Kroehnert, ESPAT-Consulting (Chair)
  • Peter Cockburn, Cohu (Co-Chair)
  • Jonathan Abdilla, Besi
  • Rolf Aschenbrenner, Fraunhofer IZM
  • Mark Azzopardi, CMT Semiconductor
  • Ruud De Wit, Henkel
  • Ivan Galesic, OSRAM
  • Michel Garnier, STMicroelectronic
  • Matthias Grossmann, Momentive
  • Ingo Henkel, Bosch
  • Frank Kuechenmeister, GLOBALFOUNDRIES
  • Cassandra Koenig, Advantest
  • Andy Longford, PandA Europe
  • Andy Miller, IMEC
  • Jens Mueller, IMAPS Europe Chapter
  • Pascal Oberndorff, NXP
  • Thomas Oppert, PacTech
  • Gabriel Pares, CEA-LETI
  • Amandine Pizzagalli, Yole
  • Klaus Pressel, Infineon
  • Roland Rettenmeier, Evatec
  • Ralf Schmidt, Atotech

See information in PDF here.
 

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Questions?

Contact Pantelitsa Markus at pmarkus@semi.org