Call for Abstracts

Power and Interconnects Innovations Enabling AI System Performance

You are now invited to submit your abstract for the 2026 Advanced Packaging Conference (APC). 

Collection will be open until Wednesday, July 1, 2026.

Advanced Packaging (AP) and test innovations are essential to sustain system-level performance scaling now that traditional device scaling alone is no longer sufficient. In 2026, AP stands at the center of next-generation electronics, enabling higher integration density, improved power efficiency, and superior thermal and signal integrity across applications from HPC and AI accelerators to automotive, 5G/6G connectivity, and edge devices. 

By leveraging technologies such as 2.5D and 3D integration, chiplet-based architecture, heterogeneous integration, and advanced substrates and interconnects, the industry can significantly boost compute, bandwidth, and functionality while limiting power consumption. Novel materials, back-side power delivery, fine pitch interconnects, and co-design across chip, package, and system are becoming key differentiators for competitive systems.

At the same time, sustainability and supply chain resilience are gaining critical importance. Advanced packaging must address lifecycle environmental impact, resource efficiency, and circularity, while supporting regional manufacturing strategies and robust ecosystems. Packaging is evolving from a traditional back-end step to a strategic enabler of system architecture, co-optimization, and differentiation for the entire electronics value chain.

At this year’s Advanced Packaging Conference (APC), we would like to present the latest advancements and innovations in these fields by bringing together leading experts, innovators, and stakeholders from academia, industry, and government to explore the latest trends, challenges, and breakthroughs.

APC thrives on collaboration and the exchange of ideas. We invite you to submit an abstract and showcase how your company contributes to this evolving landscape, whether through innovation, new technologies, manufacturing excellence, or intelligent design and testing systems.

At SEMI, we are committed to supporting this knowledge sharing that sparks new ideas to drive this industry into the next revolutionary era.

Submitted papers should cover packaging, assembly, wafer and package testing, innovation, and new developments in design, Electronic Design Automation (EDA), Assembly Design Kit (ADK), simulation, manufacturing equipment, material, and process IP, enabling heterogeneous integration in package for new applications. We encourage participation from companies and individuals that can demonstrate advancements in the following areas:

From Wafer-Level to Panel-Level

• Trends and Roadmap from Low Cost to High End: Scaling formats, Heterogeneous integration, Chiplet, Emerging technologies (fine pitch, bridge)
• European ecosystem (OSAT, Foundry, IDM) and Pilot lines
• Carrier, Substrate, and Dielectric materials for PLP (electrical, warpage)
• Equipment, process integration, and automation challenges for large panels
• Cost, throughput, and yield tradeoffs between wafer-level and panel-level 

Design Flow for Advanced Packaging (AP)

• System-level co-design and data format across chips, packages, and board for AP
• Design methodologies for chiplet-based and heterogeneous systems 
• Unified EDA flows for 2.5D/3D, fan-out, SiP, chiplets, and co-packaged optics
• Electrical, thermal, thermos-mechanical co-simulation within design flow
• AI/ML-assisted design space exploration and optimization for AP solutions
• Design for manufacturability, test, and reliability (DfM, DfT, DfR) in AP
• Assembly Design Kits (ADK) and Standards (eg, Universal Chiplet Interconnection Express – UCIe)  

Co-Packaged Optics (CPO)

• Co-packaged optics architectures for switches, data centers, and AI/HPC systems
• Integration of silicon photonics, II-VI, III-V devices, and electronics in AP
• High-accuracy assembly, alignment, and coupling techniques for photonic
• Packaging solutions for lasers, modulators, detectors, and passive photonic devices
• Thermal management, reliability, and qualification of CPO modules
• Materials and interposers (e.g., glass, silicon) tailored for photonic integration

Materials for Advanced & Sustainable Packaging

• Resource-efficient / low-waste chemistries for plating, cleaning, coating
• Materials, Process: Recyclability, CO2 footprint, environmental impact reduction
• Bio-sourced, sustainable organic packaging materials
• Low-loss dielectrics and advanced redistribution layer (RDL) materials
• Advanced IC substrate materials (organic, glass, ceramics, metal)
• High-performance mold compounds, underfills, encapsulants, Thermal Interface Materials (TIMs), heat spreaders and novel solutions for Power & HPC
• Interconnect materials/processes for fine pitch and high reliability

Inspection, Metrology, and Testing Strategies

• Scaling to large format & high- power package
• Advanced contacting solutions for unconventional and high-power packages
• Solutions for RF mmW Antenna in Package (AiP) devices
• Strategies & solutions for Wafer Level Test of 3D structures, partially assembled dies, photonics and Co-packaged optics
• Novel non-destructive methods & tools for defect detection in the AP domain
• Repair solutions in advanced packaging and IC substrate field
• AI, ML (Machine Learning), and data management solutions for optimizing Inspection, Metrology and Testing

(2026) Power Delivery and Thermal Management

• Thermal challenges in 2.5D / 3D complex multi-chip and chiplet devices 
• Novel heat dissipation and thermal management solutions for AP (eg: Liquid Cooling)
• Future materials for power and heat management
• Adoption of GaN, SiC for next HPC devices
• Backside metallization in Advanced Packaging, Wafer Level and Panel Level 
• Limits of power density and integration scaling
• Mass Production and Field-proven sustainable performance
• Simulation capabilities and limits in AP
   

Guidelines:

• The abstract should have between 250 and 500 words (starting with a descriptive paragraph identifying the issue addressed and solution). Please focus on the news instead of describing state-of-the-art.
• Please submit your abstracts online only. Abstracts submitted via e-mail, post, or other methods will generally not be accepted. Please submit your abstract, biography and a photo through our portal.
• The conference language is English.
• Abstract submission only in English.
• The submission deadline for APC is Wednesday, July 1, 2026 (midnight, CEST)
• For presenting authors of accepted abstracts, registration and participation in SEMICON Europa 2026 and/or the conference will be waived. 

Your abstract will only be included in the review process when the submission is complete.

How to submit: 

1. Click on the link: https://portal.smart-abstract.com/sceu26
2. In the Attributes, select Presentation: Paper submission (including abstract)
3. Select the Paper submission (including abstract) and choose the desired Topic:
   • Advanced Packaging Conference
4. Use the SEMICON Europa Speaker Registration Guide to help guide you, as there is now the possibility of adding 2 presenters.

Please note that only the correct abstract submission will be considered.

Evaluation criteria:

• Must include significance, usefulness for the manufacturing world, with a clear and accurate paper.  
• Abstracts will be peer-reviewed and selected relative to the points above.  
• Application related presentations, i.e., on joint projects between users and suppliers, are encouraged.
• Papers are to be non-commercial with a focus on technical/economical merits of a process rather than the individual company’s product benefits.

Notification: Selected presenters will be notified August/ September 2026.

SEMI Europe Advanced Packaging Conference (APC) Committee:

• ESPAT-Consulting, Steffen Kroehnert (Chair)
• Cosmic Services Germany GmbH, Jan de Koning Gans (Co-chair)
• GlobalFoundries, Frank Kuechenmeister (Co-chair)
• Advantest, Cassandra Koenig
• ams OSRAM Group, Ralf Wombacher
• STMicroelectronics, Jerome Lopez
• Yole Group, Emilie Jolivet
• CEA-Leti, Sylvie Joly
• Fraunhofer IZM, Tanja Braun
• Henkel, Mario Saliba
• Ruud de Wit, CITC - Chip Integration Technology Center (part of TNO)
• IMEC, Andy Miller
• Infineon, Andreas Grassman
• JCET, Roberto Antonicelli
• JCET, Mark Anthony Azzopardi
• NXP, Pascal Oberndorff
• PacTech, Thomas Oppert
• Robert Bosch, Ingo Henkel
• Atotech, Dirk Rohde
• CSA Catapult, Jayakrishnan Chandrappan
• Besi, Jonathan Abdilla
• Evatec, Andre Schenk

Questions?

Please contact SEMI Europe Programs Team at [email protected]