Michael Liehr is Vice President for Research, Associate VP for Business, Alliances and Consortia and Professor at the College of Nanoscale Science and Engineering in Albany, NY.
His technical focus at CNSE is the establishment of a Center for CMOS Derivative Development. Prior to joining CNSE, he was an IBM Distinguished Engineer responsible for strategic production alliances and factory synchronization and was a member of the IBM Academy of Technology. He holds a PhD in physics and is PMI certified, has published over 100 papers and 20 patents.

The College of Nanoscale Science and Engineering (CNSE) leverages industry partners, academic and government resources in effective partnerships to enable accelerated R&D. This unique consortium environment creates a viable financial and technical foundation that enhances knowledge-based development of integrated electronics while reducing costs.

CNSE provides facilities, tooling, a portion of operating expenses, and operates the clean-room facilities. Partners provide engineering resources, tooling, process IP to enable R&D and customize for their applications, and a portion of operating expenses. Material suppliers, government entities and other academic institutions participate as partners on a customized basis.

The existence of advanced facilities, tool and material suppliers, together with IDMs under one roof, combined with strong government support, creates a unique environment that fosters cross-partner joint development activities. The knowledge sharing and close physical proximity results in a fast and economical advanced node R&D.

The presentation will highlight the recent advanced in CNSE’s 450mm program and speak to the announcement of a 450mm consortium based at CNSE.    
 

 

Hans Lebon obtained his Master of Science in Electrical Engineering from the University of Leuven (Belgium) in 1984. He joined Imec in September 1984 as a BEOL integration engineer. From 1985 till 1989 he worked at Imec as BEOL, FEOL Logic and Memory integration engineer.
In 1990 he became responsible for operations and hardware engineering of the Imec 5” R&D line. He was responsible for the 6” conversion in 1995 and the 200 mm conversion in 1999 of the Imec R&D line.
In 2004 he became also responsible for the new 300 mm Imec R&D line.
In 2007 he was appointed Vice President Fab Operations, responsible for the 200 mm and 300 mm Imec R&D line, including facilities.
From 2009 until now, Hans is Vice President FPS, Fab and Process Step R&D&M technology unit.  
Currently Hans Lebon holds the position of Vice President FPS, Fab and Process Step R&D&M technology unit. He is responsible for unit process step R&D, Operations (200 mm and 300 mm), buildings and facilities, EHS (Environment Health Safety) and Purchase&Warehouse.

 

 

Tom Jefferson is Program Manager of 450mm Transition at SEMATECH.  He has been on assignment from Intel Corporation since June 2008. Over the past three years he has led all aspects of the 450mm transition planning effort.  Prior to his assignment at SEMATECH, Jefferson held various managerial and technical positions at Intel in the areas of factory automation, factory integration, systems engineering, wafer size conversion, industrial engineering, and material handling.  He is formally the co-chair of the ITRS Factory Integration technical working group, and a former member of the ASMC technical committee.  Jefferson holds a BS in industrial engineering from the Rochester Institute of Technology (RIT).  He is the author of 20+ publications in his areas of technical expertise.

The transition to 450mm wafer processing is no longer a question of "if".  The semiconductor supply chain ramping is now to meet the expected demand of device makers planning for the 450mm transition.  SEMATECH, its members, and partners have defined fundamental pre-competitive 450mm infrastructure and guidelines, and momentum towards realization of the 450mm transition is strong in all areas of the semiconductor manufacturing supply chain.  SEMATECH is currently working to enable 450mm equipment development by providing bare and processed silicon, and metrology capabilities, with a goal of demonstration of unit-process capability and equipment reliability to support device maker 450m pilot line startups.  A comprehensive overview of the current state of the 450mm landscape will be provided, along with the case for industry collaboration to enable a cost effective wafer size transition.

Laurent Bosson is a retired senior manager with 47 years of worldwide management experience. He has 25 years experience in senior management including: Executive VP in charge of RD & Manufacturing operations, CEO of ST Microelectronics Americas ('92 to '96) and from '96 Chairman Of the Board for the same subsidiary.
Laurent has extensive wide range of operational experiences, including: production, maintenance, product engineering and manufacturing engineering, sites and operations director.
Laurent energized 18000 employees worldwide (EU, USA, ASIA) in 2 R&D centers and 7 manufacturing technical centers, a complex and demanding global organization sharing resources and knowledge across themselves and Countries.
Having completed multiple wafer fabrication facilities projects and built high performing teams responsible for sites start up in North America, Europe and Asia; Laurent is proven and recognized as an effective leader in high-tech industry, understanding the real meaning of diversity.
He lead a team of process engineers, manufacturing & facilities experts executing the successful transfer, with automotive customers qualifications, of manufacturing operations from Europe/USA to Asia.
Laurent leads the silicon R&D International Alliance with NXP & FREESCALE for 300mm wafer size for nano technologies up to 45 nm. At the end of this Alliance, he participated to the negotiations which turned to conclude, between ST& IBM, the agreement to cooperate in the development of silicon technology CMOS Logic 32&22 nm nodes, as well as developing Differentiated Technologies together.
Laurent is an open mind leader who has the distinction of being among an elite group of executive that actually worked on the facilities floor. He started his career as production worker, then progressing through skilled trades via evening University and on to engineering and Executive Management.
Started as a worker, Laurent progressing on to the executive level coupled with his passion for People and Technologies, gave him a unique perspective and back ground as agent of Individual/Cultural changes. 
Laurent retired from ST Microelectronics in 2008, where he last served as Executive VP Front-End
Technology and Manufacturing, and Chairman of the Board, ST America.

Laurent currently is the Founder of LBConsulting firm.

Michel BRILLOUËT joined CEA-LETI in 1999 where he managed a R&D division on silicon microsystems and from 2001 also on silicon microelectronics. He is presently strongly involved in the shaping of the European Research Area in nanoelectronics (ENIAC, etc.) and in bodies targeting international collaborations. He participates in international forums (ITRS…) and conferences (VLSI-TSA, INC…).

Prior to joining CEA-LETI, BRILLOUËT worked for 23 years in Centre National des Télécommunications (CNET; France Telecom R&D Center) where he held different positions in microelectronics research. In 1992, he was assigned to the Common R&D Center between STMicroelectronics and France Télécom in Crolles, France, where he was in charge of all the technology R&D programs for the Crolles site, including CMOS, eDRAM and BiCMOS process and process integration along with their interaction with the design community.

BRILLOUËT graduated from Ecole Polytechnique in Paris in 1974 and Telecom Paris in 1976.

The transition to 450mm wafers is a major step the microelectronic industry is expected to make in the coming decade. We will first discuss the potential reasons behind this move. We will then address the question of the timeline and of the associated processes to be developed on 450mm wafers. We will conclude in discussing potential R&D models to address the huge cost of this transition.

Bernie received a Masters Degree in Engineering (MEng) from Newcastle Polytechnic and has been working at Intel for the past 14 years holding various Engineering and Management roles across all four wafer fabrication facilities. Bernie is currently responsible for all silicon nanotechnology and 450mm EU projects involving Intel Ireland. Bernie’s semiconductor career spans 24 years, with other Process and Equipment Engineering positions held at Telefunken GmbH, Nortel/Bell Northern Research, Applied Materials and Newport Wafer Fab.

SEMI Europe 

Heinz Kundert was named president of SEMI Europe in October 2005. His responsibility includes overall guidance of the SEMI activities and membership outreach all over Europe and the CIS countries and he belongs to the Global Executive Team of SEMI International.
As part of the SEMI mission Heinz Kundert is focusing on providing higher level of services for SEMI members/customers and to increase their satisfaction in Europe and CIS. To strengthen the European-based semiconductor industry by providing a valuable platform to enhance innovation and manufacturing capabilities is one of the prime goals.
Kundert has been within the semiconductor industry for 23 years when he joined Balzers in Liechtenstein, a global supplier of thin film equipment for semiconductor manufacturing and related applications. He began as a sales manager for Asia and expanded his role of responsibility through several positions within the company. In total he lived more than five years in Asia before he became COO of the newly formed company Unaxis that was a merger between Balzers and Leybold. From 2002 Kundert was named CEO of Unaxis.
During his tenure Kundert expanded business in semiconductors, optics, optical discs, hard coatings, space and vacuum with a major focus on the Asian market where he generated 50 percent of the revenue.
Kundert has a degree in mechanical engineering and business administration with a federal diploma from the FAH/University of St. Gallen, Switzerland

 

 

Silicon Systems Group, Applied Materials

Kirk Hasserjian was named corporate vice president for Silicon Systems Group Strategic Programs at Applied Materials, Inc. in October 2010.  He leads critical growth programs to improve the company’s future.  Since joining Applied as appointed vice president for the SunFab operations organization in June 2009, he has driven significant improvements.  He previously was appointed vice president and general manager of the SunFab Thin Film Solar business.
Prior to joining Applied Materials, Mr. Hasserjian served in a variety of technical and management roles, most recently as senior vice president for Global Manufacturing Operations at FormFactor, Inc.  He previously spent 25 years at Intel Corporation, where his responsibilities included leading Intel’s Flash memory technology development activities in NOR, NAND and future non-volatile memory technologies.  He also held technical and management positions in the company’s D2 development and manufacturing facility, including five years as D2 plant manager managing the facility’s factory performance and all technology module development activities.
Mr. Hasserjian received his bachelor of science degree in chemistry from the University of San Francisco and a master of science degree in chemical engineering from Stanford University.

The semiconductor industry has relied on wafer size transition as a means to improve overall costs of manufacturing.  As the overall silicon area demand increases, production at larger wafers sizes provide substantial benefits for the IC suppliers due to improved manufacturing efficiencies and overall lower die cost. Any transition of wafer size needs to be a win-win for the IC makers and the equipment industry to ensure a viable long term industry that can continue to drive innovation. Several factors dictate a successful transition for the industry as a whole.  Because the transition to 450mm requires a complete redesign of all tools in a fab, the R&D costs is substantial in terms of scope and costs.  Furthermore, the equipment suppliers need to recoup their investment across a limited number of customers as the industry consolidates.  In order to maintain the symbiotic relationship between the equipment suppliers and the ic makers, it is imperative that the transition to 450mm occurs in a coordinated fashion, with shared risks with respect to insertion timing and costs.  Finally, the overall costs of the tools to the IC makers should be commensurate to the cost of ownership offered by the tool suppliers to make this transition a true win-win proposition.

 

Peter Csatáry is Head of Group of M+W Group's Global Technology Services. He joined the company in 1989 with an industrial background in production planning and control in the semiconductor industry. Mr. Csatáry has 25 years of professional experience in or serving the semiconductor industry in functions including manufacturing planning and control, scheduling software development, wafer fab operational consulting, marketing and project management.Mr. Csatáry holds a B.Sc. in Mechanical Engineering and an M.Sc. in Industrial Engineering from the University of the Witwatersrand, South Africa.

Currently, the semiconductor industry is evaluating what the combined changes of the 450 mm wafer size transition and future advanced technology nodes will have on manufacturing facilities, both for greenfield projects as well as for potential fab conversions. The engineering and prototyping of 450 mm process equipment and automation systems is in the initial stages of development and testing, therefore it is necessary to consolidate this experience and extrapolate the potential impact of the 450mm wafer size transition with respect to the design and construction of the wafer fab’s buildings and facilities. Preliminary investigations have been performed by M+W Group, the major considerations of which are presented in this paper.

 

Graduated Electrical Engineering, Technology Dept., Yamagata Univ.
Joined Shin-Etsu Polymer in 2003 and engaged in sales and technical marketing.
SEMI membership: Silicon Wafer, Physical Interfaces & Carriers, 3DS-IC, HB-LED and Metrics.

This presentation focuses on 450mm bare wafer transportation from wafer
manufacturers to device manufacturers.
We have to understand the big difference between 450mm FOSB(Front Opening
Shipping Box) and MAC(Multi Application Carrier) in wafer support function.
450mm FOSB should be essential for 450mm bare wafer shipment for high volume manufacturing.

Graduated from Grenoble Institute of Technology (INPG) 1995 with specialization in  semiconductor physics, technology and devices, he holds a master degree in this field from Grenoble University (Joseph Fourier University) in 1995.
The same year, he entered CEA-LETI, as researcher, in the SOI material research department, managed by Dr M. Bruel, inventor of the Smart Cut technology.
He joined Soitec in 1998 in the R&D organization and held various management and project leader positions in the field of SOI, Ge, III-V and Wide band gap materials (SiC, GaN) and related engineered substrates.
Since 2009, he took the head of Soitec’s group Corporate R&D organization as Soitec’s VP, with mission to fullfill company’s long term technological needs in the field of SOI materials and III-V based engineered substrates for lighting, 3D, photovoltaic and power applications.

The Semiconductor Industry has undergone a wafer size transition about every eight to ten years. The latest wafer size transition occurred at the beginning of last decade with the introduction of production lines with 300 mm wafers in diameter. It is expected that the 450 mm transition will occur sometime in the current decade.

Silicon-on Insulator (SOI) substrates bring significant benefits to the semi-conductor industry for high performance as well as low power applications. SOI wafers will play a key role for the continuation of Moore’s law for advanced CMOS technology nodes by serving either planar and Finfet device architectures.

SOITEC is designing and producing SOI substrates of all sizes by using the industry-proven Smart CutTM technology. The presentation will focus on SOI wafer technology advantages and how SOITEC is preparing for this transition

Ines Stolberg studied Physics at the Friedrich Schiller University in Jena and received her diploma in 1988. After finishing her studies she was engaged in the development of electron-beam lithography equipment in different positions. Ines Stolberg assumed responsibility for Strategic Marketing within the Vistec Electron Beam Lithography Group in 2004.

Electron-beam lithography is one candidate for next-generation lithography (NGL) named in the ITRS roadmap. So far electron-beam direct write (EBDW) is recognized as a useful technology for fast prototyping, design evaluation and low volume production. Maintaining the pace of launching 450mm substrate dimension into the semiconductor manufacturing process, the requirements on electron-beam lithography equipment are very challenging. Full 450mm substrate exposure capability in conjunction with constantly improved lithography performance is the key development objective.  
To fulfill the lithography performance requirements completely new approaches on the lithography platform including wafer handling have to be addressed. Already today, with current 300mm wafers, accurate and reproducible positioning of the electron beam imposes major efforts. This becomes even more severe when going to 450mm wafers, due to larger travelling ranges of the stage, as well as accumulation of errors from thermal drift. 
In the presentation selected performance parameters as wafer flatness, defects, thermal wafer stability, which are all related to the ITRS lithography performance parameters are discussed.
A vacuum environment is mandatory for electron-beam lithography. Therefore, wafer clamping proceeds via electrostatic forces on an electrostatic chuck. In our approach, the electrostatic chuck is a separate unit, which is mounted kinematically on the so-called metro-box. The metro-box holds two flat mirrors arranged in an orthogonal configuration to allow the measurement of the x-y-position by interferometric techniques.
In the presentation first finite-element simulation results of the electrostatic chuck design will be disclosed. The impact of different materials and light weighting strategies on the chuck performance such as in plane distortion due to bending, have been analyzed. Thermal effects caused by the E-beam input power have also been considered and are shown to play a central role for 450mm chuck design.
Finally, first conclusions with regards to the design and manufacturing will be made.

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Graduated from Technische Universität München TUM in 1999 with specialization in  mechanical engineering, design and development, he was employed as research assistant at the Institute for Machine Tools and Industrial Management (iwb) from 1999-2005, leading the team for microassembly during the last three years. He holds a PhD (Dr.-Ing.) degree aquired 2006 in the field microassembly and non-contact handling.
Together with Josef Zimmermann he founded Zimmermann&Schilp Handhabungstechnik GmbH in the same year, a company specialized on non-contact handling using ultrasound levitation for all kinds and sizes of flat parts, including glass, semiconductor and solar wafers, metal sheets and foils.

This presentation focuses on the new possibilities using the non-contact handling with ultrasound levitation for semiconductor wafers, especially 450mm wafers.
The new wafer size requires new handling concepts with regard to bow and sag, especially regarding increasing levels of cleanliness and 3D technologies.
Employing non-contact handling technologies, full wafer support on frontside and/or backside is possible even for thinner wafers.
Non-contact handling using ultrasound levitation prevents particle contamination, generation and cross contamination. As no additional air flow is used for the supporting air film, every gas or every clean air can be used.
Additional to conventional wafer handling procedures using robot and (non-contact) gripper, the technology enables clean and gentle wafer transfer over larger distances by non-contact linear tracks. The product portfolio also includes non-contact chucks, e.g. for measurement purposes.

 

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Guy Dubois embodies more than 40 years of  worldwide level Management experience on
Manufacturing and Research and Development in semiconductor industry.

After 10 years spent on process and components research with CII and the Central research Laboratorof Thomson, he took the lead of the process engineering development of  EFCIS where he is also in charge of the process transfers from Motorola.
Then, within STMicroelectronics, he is successively Divisional Quality Director, Rennes plant
Manager, then Grenoble Operation Manager in charge of a major site restructuring.
In 1987 he is promoted Group vice President and creates the Wafer Foundry organization in charge ofworldwide ST foundry needs, then takes in charge the Manufacturing strategic projects.
From early 2007 to mid 2008 he is the Office Director of the cluster EUREKA MEDEA where he
actively participates to the definition of CATRENE and to the ENIAC launching.
Then he came back to STMicroelectronics as Technology R&D Group Vice President and IP &
Licensing Group Vice President.

In June 2009 he starts his own consulting company: GDCL Management where he supports several semiconductors companies and equipment companies. Guy is also a technical/economical expert for European Community and for the French support to SME organization named OSEO.

Guy Dubois holds several patents, including the VIAS patent used in all semiconductors processes with critical dimensions below 0.5µ.

 

 

Mrs. Maria Marced is President of TSMC Europe, with responsibility for driving the development, strategy and management of TSMC Europe.
Before joining TSMC, Maria was Senior Vice President and General Manager of Sales and Marketing at NXP Semiconductors/Philips Semiconductors.

Maria joined Philips Semiconductor in September 2003 as Senior Vice President and General Manager of the Connected Multimedia Solutions Business Unit overseeing Philips' semiconductor solutions for Connected Consumer applications.

Previous to her work with Philips, Maria was employed at Intel where she developed her professional career for more than 19 years, reaching the top position in the Europe, Middle East and Africa region as Vice President and General Manager.
Maria is currently on the EMEA Leadership council, of the Global Semiconductor Association. (GSA), advising the GSA directors on Regional and global issues..

Mrs. Marced holds a Ph.D. in Telecommunications Engineering from Universidad Politecnica de Madrid, Spain.

Looking beyond the current financial climate, it is clear that for semiconductor companies to grow and succeed, they will need to innovate and collaborate. especially for the adoption of 450mm wafer manufacturing. Maria Marced will outline her view of the current market, and show some of the ways that TSMC is collaborating with its partners and customers to unlease their innovation.
Maria will also share her vision of the challenges facing the semiconductor market as it adopts the latest technologies to 450mm manufacturing.

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Richard Öchsner received the M.S. (Dipl.-Ing.) degree in Electrical Engineering and the Dr.-Ing. degree from the University of Erlangen. Since 1991 he is with Fraunhofer IISB working in the department Semiconductor Manufacturing Equipment and Methods. He is deputy head of department and leads the group Manufacturing Control and Productivity and was/is en-gaged in the fields of semiconductor equipment assessment, contamination control in equip-ment, equipment control, integrated metrology, advanced process control, manufacturing methods, optimization, productivity and energy efficiency. He was/is involved in several Eu-ropean and national co-operative R&D projects in different functions also as coordinator. Richard Öchsner is active in SEMI standardization and a member of the Factory Integration TWG within ITRS (International Technology Roadmap for Semiconductors).

There is broad consensus among the European E&M companies that they just not should sit along the sideline and watch what is going to happen, but should actively participate at an early stage of these developments to stay competitive. Based upon a European industrial initiative from equipment and material suppliers to become active in 450mm wafer size technologies the project EEMI450 was initiated.
The project addresses the complete spectrum of E&M 450mm development: wafer manufacturing and characterization, metrology, waferhandling, automation, and development of process modules, both batch and single wafer, including the supply chain. Naturally only those metrology and process modules are in the focus of this project for which the respective partners possess key competence. The partners have opted for rather short project duration to make the first steps into the new arena, to discuss basic concepts and standards, to produce first 450mm wafers and in some cases to first prototypes and proof-of-concepts. Based upon these initial learning further efforts will be certainly needed to come to production worthy solutions. Intel as a consortium member is an important driver of the global 450mm activities and will provide guidance to the project in view of specifications, standards and concepts. In this presentation first results will be presented.
This project is funded by the ENIAC Joint Undertaking (JU) and eight national public authorities.