New Materials Session - Abstracts and Biographies
Fabrice Letertre, VP, Corporate R&D
Soitec
Biography
Graduated from Grenoble Institute of Technology (INPG) 1995 with specialization in semiconductor physics, technology and devices, he holds a master degree in this field from Grenoble University (Joseph Fourier University) in 1995.
The same year, he entered CEA-LETI, as researcher, in the SOI material research department, managed by Dr M. Bruel, inventor of the Smart Cut technology.
He joined Soitec in 1998 in the R&D organization and held various management and project leader positions in the field of SOI, Ge, III-V and Wide band gap materials (SiC, GaN) and related engineered substrates.
Since 2009, he took the head of Soitec’s group Corporate R&D organization as Soitec’s VP, with mission to fullfill company’s long term technological needs in the field of SOI materials and III-V based engineered substrates for lighting, 3D, photovoltaic and power applications.
New Material Challenges in 32nm Gate First High K Module
Falk Graetsch, Principal Member Technical Staff and Rick Carter, Senior Member Technical Staff and FEOL Integration Manager
GLOBALFOUNDRIES
GLOBALFOUNDRIES
Biography
After his Diploma in Microelectronics and Semiconductor Technology, Falk Graetsch joined ZMD Dresden in 1986 as an engineer for physical analysis and began later as a CVD process engineer. From 1991-1993 he worked at Eurosil as a diffusion process engineer. After 1993 he was a diffusion process engineer at EM Microelectronic-Marin. In 1997 he joined AMD Dresden (now Fab1 of GLOBALFOUNDRIES) where he has since been working as a diffusion process engineer in different areas for both manufacturing and process development: furnaces, cleans, metrology, silicon and other materials, RTA, HK-deposition. Since 2009 he is a principal member of technical staff and coordinates new process introduction.
Rick Carter is a senior member of technical staff and FEOL integration manager at GLOBALFOUNDRIES. After his PhD in 1999, he joined IMEC in Leuven, Belgium as a researcher and postdoctoral fellow focused on integration and characterization of high-k dielectrics. From 2003 to 2006 he was with LSI Logic in Gresham, OR where he worked as the project manager for a joint development program exploring the integration of carbon nanotube-based devices onto a CMOS platform for non-volatile memory applications. Since May 2006 he has been with GLOBALFOUNDRIES (formerly part of AMD) working on the integration of high-k/metal gate technologies for CMOS applications.
Rick Carter is a senior member of technical staff and FEOL integration manager at GLOBALFOUNDRIES. After his PhD in 1999, he joined IMEC in Leuven, Belgium as a researcher and postdoctoral fellow focused on integration and characterization of high-k dielectrics. From 2003 to 2006 he was with LSI Logic in Gresham, OR where he worked as the project manager for a joint development program exploring the integration of carbon nanotube-based devices onto a CMOS platform for non-volatile memory applications. Since May 2006 he has been with GLOBALFOUNDRIES (formerly part of AMD) working on the integration of high-k/metal gate technologies for CMOS applications.
Abstract
32nm Gate First High-K/Metal Gate technology is now in mass production at GLOBALFOUNDRIES Fab1 manufacturing site in Dresden, Germany. In this presentation, we will give an overview of the new materials and processes that were introduced in order to meet the technology requirements for high performance CMOS devices. In addition, some of the associated challenges with high-k/metal gate process integration will be discussed.
Guenther Ruhl, Principal New Materials
Infineon Technologies AG
Biography
Guenther Ruhl is Principal for new materials at Infineon Technologies AG in Regensburg, Germany. He studied chemistry at the Technical University of Munich where he received his Ph.D. in material chemistry. He gained experience in semiconductor technology for 20 years in several positions at the Fraunhofer-Institute for Solid State Technology and Infineon Technologies. He worked in the fields of deposition, characterisation and plasma etching of several thin film materials as well as in metallization integration and photomask technology. Currently he works on high-k dielectrics and carbon as electronic material. He is author and co-author of over 40 technical papers and 15 patents.
Abstract
Proceeding integration density of ICs poses increasing requirements for capacity density of integrated capacitors for the “More Moore” as well as the “More than Moore” approaches. Since increasing the capacitor area faces technological limits, the introduction of high-k dielectric materials into integrated capacitor technology is the objective of a MEDEA+ project called “MaxCaps”, which proceeds from 2008 to mid 2011. The main project goal is the development of dielectrics with very high dielectric constants and suitable deposition processes (ALD, MOCVD) for the fabrication of high-density 2D and 3D capacitors.
This talk gives an overview on the results gained for a variety of applications, namely DRAM capacitors, RF capacitors, and high-voltage capacitors.
This talk gives an overview on the results gained for a variety of applications, namely DRAM capacitors, RF capacitors, and high-voltage capacitors.
Materials for Next Generation Phase Change Memories
Mauro Alessandri,Technology Development Manager; co-author: Roberto BEZ
Micron Semiconductor Italia
Biography
Mauro Alessandri is Technology Development Manager at Micron Semiconductor Italia, Agrate Brianza, Italy . His focus is on the R&D of diffusion, CVD, ALD and wet technologies. Prior to joining Micron, Mr. Alessandri served as a Technology Development Manager at STMicroelectronics and Numonyx. He holds 7 patents related to process technology and is author of more than 100 papers. Mr. Alessandri received a M.S. in physics from University of Milan, Italy. He is active member of the Front End working group in the ITRS Roadmap Organization.
Abstract
Industrial exploitation of chalcogenide materials is in place since many years in the optical field for the rewritable compact disk applications. As a consequence the research and development efforts have been greatly focused in this direction, mainly studying the optical behaviors. Only recently the use of chalcogenide materials to realize phase change memories has been proposed with the aim to have high performances and high density non-volatile memories. Although the phase change memory concept has demonstrated to be very solid and the phase change memory technology has reach very good maturity level, the introduction in the memory market has not yet happened. The main reason is related to the continuous scaling of the industry standard memories, either DRAM or Flash, well beyond what was forecasted. Nevertheless the development of phase change memories is constantly increasing with the aim to become a mainstream technology. For this reason there is a constant intense effort on the phase change memory technology development and on the chalcogenide material characterization and in general on the exploration of new materials. This presentation will review the main development lines adopted for the process integration and for the exploration of new materials
Organic and Oxide Transistors and their Application in Flexible Displays, Memories and Circuits
Gerwin H. Gelinck, Program Manager
Holst Centre / TNO
Biography
After his Ph.D Gerwin Gelinck joined Philips Research as a Senior Scientist in 1998 where he started working on polymer and organic transistors and their use in integrated circuits, displays and memories. In 2002 he was co-founder of Polymer Vision. From 2002 to 2006 he was Chief Scientist of Polymer Vision. Since 2007 he is program manager at the Holst Centre, a joint research initiative of TNO and Imec.
Abstract
Industry analysts see great opportunities for flexible electronics, an emerging field with a growing number of applications in a variety of areas. In this presentation, we demonstrate how this technology can be used for the development of new applications. In particular, we focus on their employment in two different fields: flexible optical displays (i.e., electrophoretic displays and organic light emitting displays) and low-cost (digital and analog) microelectronics circuits (such as RFID tags, amplifiers, and display row drivers). For these examples, we elaborate on their potential, on the manufacturing approach, on state-of-the-art devices, and we discuss future challenges.
FD SOI for Low Power System on Chip
Michel Haond, Program Manager
STMicroelectronics
Biography
Graduated as engineer in 1978 from the Ecole Nationale Supérieure des Télécommunications in Paris. He joined the Centre National d'Etude des Télécommunications (CNET) for France Telecom in Bagneux/ Paris, where he worked on III-V laser diodes. In 1981, he moved to CNET Grenoble/Meylan developping RTP processes and SOI material processing. He then worked on Advanced CMOS both on bulk Si and SOI leading the activities on Advanced Devices. In 1997, he conducted the development of the 0.18µm and 0.15µm CMOS as assignee to STMicroelectronics/ Crolles before joining STMicroelectronics Crolles where he led the R&D Group for Advanced Devices and Interconnects. He was R&D Program Manager for the 90nm CMOS and then for the 45nm & 40 nm. He is currently the Director for the FDSOI/UTBB Process Integration for 28nm and for advanced device activities (20 and 14nm)
He has authored/co-authored more than 100 Technical Papers and given a dozen invited talks. He has written or taken part in more than 25 patents. He has served as a member of the Scientific Committee of different International Conferences: ESSDERC, IEDM. He is presently Member of the IEDM Subcommittee on CMOS Devices and Technology. He acted as Work Package Leader and Member of Technical Management Committees of European Projects on advanced CMOS nodes. He was invited as Rump Session panellist at the 2011 VLSI Symposium on Technology in Kyoto, Japan, dealing with the use of FinFETs or FDSOI/UTBB for the next nodes.
He has authored/co-authored more than 100 Technical Papers and given a dozen invited talks. He has written or taken part in more than 25 patents. He has served as a member of the Scientific Committee of different International Conferences: ESSDERC, IEDM. He is presently Member of the IEDM Subcommittee on CMOS Devices and Technology. He acted as Work Package Leader and Member of Technical Management Committees of European Projects on advanced CMOS nodes. He was invited as Rump Session panellist at the 2011 VLSI Symposium on Technology in Kyoto, Japan, dealing with the use of FinFETs or FDSOI/UTBB for the next nodes.
Abstract
With the advent of ever more powerful handsets like smartphones and tablets the market is looking for fast application processors (CPU & GPU) with a controlled power consumption (active and passive). Fully Depleted Silicon On Insulator (FDSOI), thanks to drastically reduced silicon and Buried Oxide thicknesses, provides excellent electrostatic control of the channel of the transistors and allows to maintain the shrink trend of Moore’s Law opening a new way to reach those high performance needs. Moreover, alternatives are opened with FDSOI to work at lower supply voltages and still maintaining the performance. This will allow reducing power consumption in a lot of applications pushing the trend towards sustainable development in upcoming circuits.
The specific electrostatic of the FDSOI devices will be developed and its specific contributions to the CMOS evolution and the prospected performance gain will be developed. The FDSOI cost impact will be discussed.
The specific electrostatic of the FDSOI devices will be developed and its specific contributions to the CMOS evolution and the prospected performance gain will be developed. The FDSOI cost impact will be discussed.
Graphene - Prospects and Potential for Future Applications
Daniel Neumaier, Head of Carbon-Electronics Group
AMO
Biography
Daniel Neumaier studied physics at the TU Munich and received his PhD from the University Regensburg. Since 2009 he his head of the graphene-electronics group at AMO GmbH. He has managed several national research projects on graphene, has been the coordinative manager of the FP7-STREP project GRAND and is member of the flagship initiative GRAPHENE-CA.
Abstract
Graphene, the two dimensional arrangement of sp² hybridized carbon atoms, has become the rising star on the material horizon for the beyond CMOS era. This hype is based on outstanding properties like high charge carrier mobility, the thin body of Graphene and the possibility to use conventional planar patterning technologies. In this talk I will give an overview on potential applications and the main challenges which have to be solved before integrating the rather unconventional material graphene in conventional CMOS technologies.
Hafnium -Based Gate Dielectrics for High Performance Logic CMOS Applications
Torben Kelwing, Group Functional Electronic Materials
Fraunhofer CNT
co-authors: B, M. Trentzsch, A. Naumann, B. Bayha, F. Graetsch, Herrmann, B. TruB, C. Klein, R. Carter, R. Stephan, P. Kücher and W. Hansch.
Fraunhofer Center Nanoelectronic Technologies (CNT), Dresden, Germany,GLOBALFOUNDRIES Dresden Module One LLC & Co KG, Dresden, Germany, University of the German Federal Armed Forces Munich
Fraunhofer Center Nanoelectronic Technologies (CNT), Dresden, Germany,GLOBALFOUNDRIES Dresden Module One LLC & Co KG, Dresden, Germany, University of the German Federal Armed Forces Munich
Biography
Torben Kelwing studied physics at the RWTH Aachen as well as the University of Manchester and received a Diploma degree from the RWTH Aachen in 2007.
He is currently PhD student at Fraunhofer CNT Dresden working in close collaboration with GLOBALFOUNDRIES Dresden technology & integration department.
His work is focused on process integration of Hf-based gate dielectrics for high-performance CMOS applications.
Before joining Fraunhofer CNT at the end of 2007 he worked as research associate and student research assistant in the CMOS group of the Advanced Microelectronic Center Aachen (AMICA) carried by the AMO GmbH. His key activities at that time were focused on investigations of lanthanoideoxides as high-k gate dielectrics.
Abstract
Future scaling of CMOS technology requires high-k (HK) dielectrics with metal gate (MG) electrodes to realize higher gate capacitances and adequate low gate leakage currents. Therefore general process integration topics such as comparison of various Hf-based gate dielectrics and different deposition techniques (MOCVD, ALD and PVD) will be discussed. A 32 nm high-k/metal gate SOI CMOS process has been applied to fabricate high performance logic transistors. Optical thickness measurement and electrical device and reliability parameters such as leakage current, capacitance equivalent thickness (CET), TDDB and ION-IOFF performance have been taken into account to compare different deposition techniques. Changes of physical material properties have been studied using atom probe tomography (APT), RBS and XPS as well. Subsequently further CET scaling capability using dedicated post deposition annealing or post work function annealing steps under N2 or NH3 ambient will be presented. Besides an overview of possible future gate dielectric scaling options will be given.
This work was funded in line with the technology funding for regional development (ERDF) of the European Union and by funds of the Free State of Saxony (P100064806). The authors are responsible for the content of this abstract.
This work was funded in line with the technology funding for regional development (ERDF) of the European Union and by funds of the Free State of Saxony (P100064806). The authors are responsible for the content of this abstract.
Engineered Substrates for Enhanced Growth of III-Nitride Semiconductors
Eric Pabo, Business Development Manager
EV Group
Biography
Eric Pabo is the business development manager for MEMS for EVGroup, prior to accepting this position he was the bonding applications engineer for North America for EV Group. Before joining EVG he spent 5 years working on wafer level packaging and assembly processes for Agilent Technologies. He has over 20 years experience in electronics manufacturing, is a professional engineer registered in the State of Colorado, is finishing his Six Sigma Black Belt Certification and earned a Bachelor’s Degree in Mechanical Engineer from Colorado State University.
Abstract
Nitride-based compound semiconductor devices show fast progress for light emitting diodes (LED), laser diodes, high-frequency transistors, power electronics and solar cells. The gain in efficiency and/or speed of these devices has mostly been enabled by recent advances in material design and growth technology. However, many applications are still suffering of reduced yield, a fact that is mostly stemming from reduced material quality and homogeneity. While high-quality substrates for homo-epitaxy are still expensive, alternative growth substrates show an offset in material properties such as lattice matching and coefficient of thermal expansion. As a result, the epitaxial film quality suffers a high dislocation density, resulting in reduced electrical and optical quality of the later-on devices.
Different solutions have been investigated in order to meet the demand for high structural quality of grown compound semiconductor films. Patterned sapphire substrates, for example, show a very beneficial effect to both the structural quality as well as the extraction efficiency of GaN-based white LEDs. The trend is leading to structure sizes in the sub-µm regime. In this way the growth time for a coalescent layer can be dramatically reduced leading to a more economical growth process. On the other hand nanostructures can also be used for epitaxial layer overgrowth, another technique to reduce the defect density of the grown compound semiconductors. Cost-efficient manufacturing of such nanostructures over the whole wafer surface is a challenge for these technologies. Here nano imprint lithography can be used as a cost-efficient way to replicate nanometre patterns over a large area.
Another technological approach for the fabrication of engineered substrates and improved layer quality is direct wafer bonding. Direct wafer bonding is a technology to join two substrate materials with different structural properties. Additionally, plasma activation of both wafer surfaces can be used to change the surface chemistry of both materials and therefore reducing the bonding temperature. In this way, materials supporting a high crystal quality of compound semiconductors can be joined with a carrier that accounts for differences in thermal expansion.
Another technological approach for the fabrication of engineered substrates and improved layer quality is direct wafer bonding. Direct wafer bonding is a technology to join two substrate materials with different structural properties. Additionally, plasma activation of both wafer surfaces can be used to change the surface chemistry of both materials and therefore reducing the bonding temperature. In this way, materials supporting a high crystal quality of compound semiconductors can be joined with a carrier that accounts for differences in thermal expansion.
This contribution will present processing solutions for the manufacturing of such engineered substrates. We will treat individual process steps for both nano-patterned sapphire substrates as well as engineered substrates formed by direct wafer bonding.
