Advanced Packaging Conference - Abstracts and Biographies

Andy Longford, Senior Consultant
Interplex Engineered Products

Biography

Andy Longford is Senior Consultant at PandA Europe, a European technical & market consultancy company involved in Semiconductor chip Packaging and Electronics Interconnection. He is Chair of the SEMI Europe Advanced Packaging Committee and is a member of the SEMI European Standards Committee. He also serves as member of a number of technical committees in UK relating to electronics interconnection technology development. He has published a number of technical papers including Packaging for MEMs, RF components and Molded interconnect devices and has presented Papers at conferences in USA, Europe and SE Asia.

Challenges and Opportunities in Advanced Packaging

Jan Vardaman, President

TechSearch International

Biography

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987. She is co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & FAB/Circuits Assembly Magazine, and the author of numerous publications on 3D packaging. She is a member of IEEE CPMT, IMAPS, MEPTEC, SMTA, and SEMI.
Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium

Abstract

Advanced packaging continues to see strong growth, especially in flip chip bumping and wafer level packaging. As the industry moves to low-k and ultra low-k devices there are an increased number of challenges in the packaging and assembly of semiconductor devices fabricated with these new dielectrics, especially with Pb-free bumps and fine pitch bumps such as copper pillar. Larger die sizes require new wafer level packaging processes. Trends in the adoption of 3D packaging with through silicon vias (TSVs) may also require new developments in materials and processes for packaging and assembly. This presentation focuses on key developments in advanced packages and challenges and includes a discussion of the opportunities created in addressing these challenges.

3D Wafer Level Packaging - Requirements & Technical Approaches

Juergen Wolf, Head of Devision HDIWLP / ASSID

Fraunhofer IZM

Biography

M. Juergen Wolf received a M.S. degree in Electrical Engineering. In 1994, M. Juergen
joined Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin and has
worked e.g. as group & project manager in the field of wafer level packaging and system
in package (SiP). Since 2011 he is head of department HDI&WLP/ASSID, responsible
for the coordination and management of ASSID - “All Silicon System Integration
Dresden-ASSID” with its 300 mm Wafer Level Integration.
He manages as well as participates in a number of research projects on European and
international level. M. Juergen Wolf is a European representative in the technical
working group Assembly & Packaging of ITRS, JEC, JIC and a board member of
EURIPIDES as well as member of IEEE and SMTA. He has authored and co-authored
more than 50 papers and reports to microelectronic packaging and holds a number of
patents.

Abstract

3D Integration is a major driver for multi-functional smart systems in the context of energy efficient and environmental friendly electronic systems in e.g. automotive, communication, industrial and medical applications. Hereby, chips are stacked and interconnected vertically to minimize electrical path lengths and thus enhance the electrical and thermal performance as well as minimize the overall package size. At the same time, advanced 3D Integration provides the opportunity to integrate electronic devices of different technologies such as MEMS, memories, digital signal processors, transceivers. This so-called “heterogeneous integration” results in advanced 3D System in Package solutions (SiP) which require the combination of different integration approaches.
3D integration is seen as one of the key technologies by ITRS, SEMATECH and others, to address high performance, high miniaturization and lower cost. The 3D technology platform comprises processes such as wafer thinning, Through-Silicon-Via (TSV) formation, TSV filling and 3D stack formation. Beside the development of new processes and the implementation of new materials 3D integration requires an overall approach which includes design and reliability tasks. The presentation will focus on key processes for the realization of 3D WL SiPs.

Fine Cu Wire Bonding in High Volume Manufacturing

Kay Essig, Technical Program Manager

ASE

Biography

Kay Essig studied Chemistry and did PhD thesis in the field of physical, theoretical chemistry. He is in the electronics industry since year 2000, the first ~7 years 2000-2006 in the PCB industry, then joined ASE in 2007 till today.
In ASE he started off in the substrate business but pretty soon got involved in all kinds of projects in regards to chip packaging, from wire bond on lead frame to fan out WLCSP. His title in ASE is Technical Program Manager.

Abstract

Wire bonding is still by far the most widely used method of die to substrate interconnection method and is likely to retain that dominant position for years to come. The explosive growth of the gold commodity price is however forcing a change in materials from gold wire to copper wire. Copper wire bonding is not new per say but it had not been used for fine pitch wire bonding e.g. wire diameters below 1.2 µ because of a number of challenges like copper oxidation, hardness, corrosion and slow intermetallic compound growth. Additional challenges arise from the advancing wafer nodes and the concomitant, ever more fragile materials. Above recent events have led to many new fundamental studies on the copper wire bonding mechanism and bond reliability. From a manufacturing perspective the focus has been to develop a repeatable and reliable process. Here, we will describe the methodology for developing a highly reliable process and we will present long term reliability test results. The later data is collected as part of reliability process/product monitoring and shows that copper wire bonds can exceed the typical JEDEC requirements by four to six times. These results apply to all commonly used package types as well as to 40/45 nm wafer node. The latest process development activities are focusing on stacked die packages with copper wires. It will be demonstrated that very low wire loops can be formed in copper wire without breaking the wire neck and with long overhangs without cracking the die. Lastly, a process for reverse bonding has been developed as well for copper wire enabling die to die bonding.

New trends in Power Electronics Packaging

Karsten Guth, Niels Oeschler, Maik Lohmann, Lars Böwer, Roland Speckels
Infineon Technologies AG

Biography

Karsten Guth studied physics with a main focus on material science at the University of Göttingen. In 2004 he joined the Technology & Innovation department of Infineon Technologies at the power electronics segment in Warstein. For the following years he focused on the development of new packaging technologies for long lifetimes and high application temperatures. Since 2011 Karsten Guth keeps the overall responsibility for the Packaging Technology team in Warstein.

Abstract

Today innovation in power electronics packaging is basically driven by the need of increased lifetimes, higher operation temperatures and increasing power densities. To pave the way for these improvements new standards in power electronics packaging are urgently needed.
While for example soft soldering and aluminium wire bonding basically limit the maximum junction temperature to about 150°C, technologies like diffusion soldering, silver sintering and copper wire bonding provide a new basis for 200°C applications.
In order to develop an understanding how to improve the lifetime of actual power modules, it will be shown that the lifetime of today’s packaging technologies is not limited by the process parameters, but by the used material combinations. Based on this knowledge we will demonstrate that the key factor for a lifetime improvement is the use of technologies with superior packaging materials.
While in silver sintering a silver powder which is located between chip and substrate is pressure sintered at high pressure (p30MPa) and moderate temperatures (T250°C) to form a compact and high melting joint, diffusion soldering utilises the concept of phase formation to form a stable joint from a high and a low melting metal. Both technologies push the remelting temperature of the established joint far beyond 200°C.
As a front side interconnect copper wire bonding combines the high degree of automation of standard wedge bonding processes with material parameters that indicate a huge increase in the load limit for thermo-mechanical stresses.
To illustrate the opportunities of these new power module packages a comparison of the reliabilities in power cycling tests with standard packages will be presented. It will be shown, that with a combination a high reliable front side interconnect and a new chip-to-substrate joint the failure mechanism can be shifted to a functional failure of the used ceramic substrates.

Industrialisation of Power Inverters and Converters for Hybrid Electrical Vehicles

Roberto Tiziani, PowerTrain Technologies and Materials manager

Magnetti Marelli

Co-author: Dr. Xinpei Cao, Application Engineer, Henkel

Biography

Roberto Tiziani was born in 1958 and he got the degree in Solid State Physics at University of Milano ( Italy ) in 1983. He joined a semiconductor company in 1985 as IC packaging engineer doing structural mechanical analysis and thermal simulation first and later in the reliability and design of plastic packaging for power and sensor application.
In 2009 he joined Magneti Marelli Powertrain group as packaging engineer on power inverters for HEV/BEV projects.

Xinpei Cao was born in 1975. She joined Henkel in 2007 as application engineer and is working in the field of die attach paste. Her current research interest includes Ag sintering paste and high thermal conductive polymer based die attach. Prior to joining Henkel, Xinpei Cao spent 2 years working on organic photovoltaic devices for IMEC, Belgium. Xinpei Cao received her Ph D Degree in Polymer Science from Zhejiang University, China.

Abstract

The thermal and electrical requirements for power control circuits used in Hybrid Electrical Vehicles ( HEV ) and Battery Electrical Vehicles ( BEV ) are becoming more critical. Junction temperatures are of the order 150C . Current manufacturing solutions utilise solder and pressure sintering for the die attach which dictates difficult and expensive processing. This paper describes the development, industrialisation and reliability of pressure less silver sintering for the attachment of active devices for in line processing.

Sinter Glue – New Horizons for Semiconductor Packaging

Thomas Krebs, Application Engineer

W.C. Heraeus

Biography

Diploma of Industrial Engineer, University of Applied Sciences Aschaffenburg
Engineer for Hardware Reliability, Daimler Chrysler AG
Application Engineer for Semiconductor and Packaging Products, W.C. Heraeus GmbH
Project leader development project for packaging material, W.C. Heraeus GmbH
Head of Customer Application for Power and Discrete Packaging Materials, W.C. Heraeus GmbH

Abstract

Since the late eighties conductive adhesives are more and more used in electronic industries for die attach on lead frames or hybrid circuit assembly. Reasons for the utilization of conductive glues are designable material properties which will lead to wide process windows of adhesives.
Silver filled conductive adhesives are green materials. They are halogen and lead free. As additional advantage the curing temperatures are moderate. The majority of today’s conductive adhesives are commonly cured at a low temperature range of 120-180°C. Consequently the thermal stress applied to the devices is much lower compared to soldering with frequently used solder alloys. Furthermore, adhesives are more flexible than solders. Especially for larger dies this flexibility provides an improved compensation of thermo-mechanical stress compared to solders. At the same time the thermal resilience as well as the thermal fatigue resistance is higher compared to lead free solders. Adhesives, providing working temperatures (long term thermal resilience) around 200°C, are available at the marked.
Due to the reason of limited electrical and thermal conductivity conventional conductive adhesives are used for applications with low power density only.
Novel silver sinter adhesives combine the positive properties of conductive adhesives like flexibility and low process temperature with highest thermal and electrical conductivity. These so called Silver Sinter Glues have a thermal conductivity comparable with solders as well as satisfying shear strength at 260°C. This new development tackles the challenge of increasing power densities by shrinkage of packages and increase of power.
This paper will present the material behavior and properties of the silver sinter glue. Additionally, the compatibility of this novel material with today’s assembly technology will be demonstrated.

Low Temperature Glass-Thin-Films for Use in Power and Sensor Applications

Jürgen Leib, Business Development
MSG Lithoglas

Biography

Jürgen Leib, Business development at MSG Lithoglas AG, Berlin; Diploma and PhD in Physics (Universität Bayreuth); 15 years international experience and in depth expertise in markets and technology of Wafer-Level-Packaging for optical applications; inventor of via-last approach for image sensors; holds more than 30 patents.
Ulli Hansen, Chief of Operations at MSG Lithoglas; Diploma and PhD Microsystemc technology (TU Braunschweig); technology expert for microsystems, measurement systems, CAD and IT with more than 10 years experience,
Simon Maus, Process- and material development at MSG Lithoglas, technology expert for wafer deposition processes incl. electroless and electrodeposition and analytics
Michael Toepper, Group Manager Photolithography and Thin-Film Polymers at Dept. High Density Interconnect & Wafer Level Packaging at Fraunhofer IZM, Berlin; international expert for wafer-level-packaging, photoresist processing, photosensitive polymers incl. BCB and Pl

Abstract

Power generation and storage, electro mobility and mobile applications are driving the increasing demand for power electronics and foster the use of cost-effective packaging without compromising on reliability and performance of advanced power semiconductors.
In this paper we describe a novel technology to manufacture robust and reliable borosilicate thin-films with CMOS back-end compatible processes. This allows bringing the benefit of glass-passivation to volume production and enables the use of wafer-level packaging and redistribution for applications in harsh environment.
Due to its excellent physical properties borosilicate glass is a very suitable material for electronic packaging. Its chemical inertness, its good electrical performance as well as its hermetic protection allow for a wide range of applications.
Using a plasma-enhanced deposition process (Lithoglas process) it is now possible to form dense, pin-hole free and hermetic borosilicate thin-films, which can be structured by standard lift-off lithography. The glass haze generated by evaporation condensates on the substrate materials at temperatures below 100 °C and is simultaneously compacted by a plasma ion source. Layers with all the beneficial properties of the bulk material may be deposited at rates of about 0,3 µm/min on a wide variety of substrate materials. Typical layer thicknesses range from about 100 nm to a few 10 µm with an uniformity as good as 1 % on a 6” wafer.
The microstructuring of these layers is done by lift-off with lateral dimensions of a few microns to several centimeters with maximum aspect ratios of approx. 2:1.
The borosilicate thin-films yield breakdown voltages as high as 250 V/µm and a typical specific resistance of 1E17 Ohm/cm at room temperature, a value which is very close to the specific resistance of bulk borosilicate glass.
The coefficient of thermal expansion of the borosilicate thin-film (3.2 ppm/°K) is match to silicon and enables systems to be reliable at high temperatures or in temperature cycling. Microstructured glass films were tested under extreme conditions e.g. up to temperatures as high as 650 °C as well as long-term temperature-humidity storage (85°C, 85% for 8000h).
We demonstrate the use of borosilicate thin-films as inter-dielectric layer in wafer-level redistribution, replacing standard polymers such as BCB or PI as a drop-in solution. Process parameters and reliability results are discussed.

Using Wafer Applied Underfill for 3D Packaging

Kenneth June Rebibis, Thinning Stacking and Package Integration
IMEC

Biography

Kenneth June Rebibis – is a researcher for the 3D Thinning, Stacking and Packaging Integration Group at Imec Belgium.

Antonio La Manna – is the team leader for the 3D Thinning, Stacking and Packaging Integration Group at Imec Belgium.

Carine Gerets – is process assistant for the 3D Thinning, Stacking and Packaging Integration Group at Imec Belgium.

Eric Beyne – is the 3D Program Director at Imec Belgium.

Abstract

The underfill material is one of the most critical parts of standard flip chip packaging. The selection of the right material is fundamental to ensure the reliability and cost effectiveness of the package. The complexity of this selection increases in case of 3D stacking and 3D packaging. To realize 3D stacking the bump pitches and the underfill gaps are scaled down to as low as possible, this results in increasing assembly complexity and making more evident the limits of standard capillary underfill. In view of this increased complexity the wafer applied underfills can offer a suitable solution. In this paper we report on the assessment done for several wafer applied underfill materials, the differences in the application process, the filling capabilities and stacking process. Finally, the interaction of the stacked dies (3D stack), packaging processes and materials are discussed. The test vehicles used for this work have bump pitches that vary from 50μm to 20 μm, the underfill gap is 13.5 μm and the bumps metallurgy is Cu and Cu/Sn. The 3D stacks have been assembled using several underfill materials, and lately electrically tested and analyzed by known reliability and quality methods such as SAM (Surface Acoustic Microscopy) Inspection, X-SEM (Scanning Electron Microscope) and Temperature Cycling Test. Primary Author: Kenneth June Rebibis Company: IMEC- Leuven, Belgium.

Low Rth Chip Interconnect for High-Brightness LED

Klaus Mueller, Development engineer
OSRAM Opto Semiconductors

Biography

Klaus Mueller has a PhD in Material Science and more than 10 years experience in research and development of soldering techniques. Since 5 years he is responsible for LED die soldering processes at OSRAM Opto Semiconductors GmbH.

Matthias Knoerr is responsible for advanced die attach techniques at OSRAM Opto Semiconductors GmbH.

Abstract

Thermal management is an essential topic in the design and application of high-brightness LED devices. A chip interconnect technique with low thermal resistance is one of the important measures to reduce the junction temperature of the LED chip and helps to improve the reliability and lifetime of the device and enlarges the potential field of application.

The current contribution focuses on the benefits and drawbacks of different die attach techniques currently used high-brightness LED, like thermal conductive glue, reflow- and thin-film soldering, low temperature sintering, flip-chip bonding etc.

Different options for characterization and process control are also discussed, including X-ray techniques, ultrasonic scanning, electrical and optical characterization.

Jens Müller, Professor

Ilmenau University of Technology

Biography

Jens Müller received his diploma degree for electrical engineering and the doctoral degree from Ilmenau University of Technology, Ilmenau, Germany, in 1992 and 1997 respectively. From 1997 to 2005, he held managing positions in development departments at Micro Systems Engineering GmbH, Berg, Germany. In 2005, he returned to Ilmenau University of Technology to establish the junior research group “Functionalised Peripherics”. In July 2008 he was assigned full professor for the department of Electronics Technology at the same university. His research interest covers functional integration for ceramic based System-in-Packages considering aspects of harsh environmental use, and high thermal / high-frequency requirements.

The Building Flavors of the “Mid-End"

Eric Mounier, Senior Analyst
Yole Développement

Biography

Dr Eric Mounier is Senior Analyst at Yole Development, a market research company based in France. Dr Eric Mounier is Responsible for MEMS & Advanced Packaging Equipment & Materials analysis. He has performed more than 100 market & technical analysis related to the micro & nanotechnologies. He is author of numerous reports on MEMS Markets trends. He is also Editor-in-Chief for Yole Media activity. He received his PhD degree in Semiconductor from National Polytechnic Institute of Grenoble.

Abstract

Wafer-level-packages have emerged as the fastest growing semiconductor packaging technology with more than 27% CAGR in unit shipments over the next 5 years to come. Rather than a single solution, wafer-level-packaging technologies are an array of solutions: historically supported by the market growth in flip-chip wafer bumping with electroplated gold, solder bumps and today copper pillars, wafer-level-packages are actually coming in many different flavors, namely Fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D Glass / Silicon interposers and of course 3DIC integration with TSV interconnects. As this wafer-level-packaging industry develops over time, we are observing that a real infrastructure has emerged by itself into what is now being called the “Mid-end” of the semiconductor manufacturing environment. Indeed, wafer-level-packages are true “Mid-end” technologies in the sense that they can all be served in the ‘blur zone’ of overlap between the IDMs or CMOS foundries' back-end-of-line (BEOL) wafer fabs and the back-end wafer bumping assembly facilities of the OSATs and wafer bumping houses. It’s worth noting that there’s a significant difference in how manufacturing is generally performed in the front-end versus in the back-end worlds. The back-end has generally a much greater cost sensitivity but can face scaling issues with time when semiconductor ICs continue to reduce in chip size while increasing in pin-count number. On the other hand, front-end related technologies are more expensive initially but could be preferable because of higher repeatability, yield, throughput and because of better perspectives in the long run when it comes to be able to scale down the technology to smaller pitch dimension while maintaining cost pressure.
For the first time, Yole’s analysts have been able to gather all the information necessary to benchmark and compare all the different alternatives offered by the present equipment and material tool-box for wafer-level-packaging. All main scenarios are analyzed, including flip-chip wafer bumping trends, Fan-in WLCSP, 3D WLP, FOWLP, 2.5D silicon interposers, 3DIC Via Middle & Via Last process scenarios. The analysis also include an specific focus on future trends for PANEL scale packaging such as Embedded die in PCB, FOWLP 2nd generation and poly-silicon or glass sheet interposers based on LCD / PCB / Solar infrastructures.

ECP® – Embedded Component Packaging Technology

A.Kriechbaum, M.Biribauer, N.Haslebner, H.Stahr, M.Morianz
AT&S Austria Technologie und Systemtechnik AG

Biography

Arno Kriechbaum is Project Leader for application projects in the Business Line Advanced Packaging at AT&S AG. He works with AT&S since 2001 and started in the Research and Development department with the evaluation and implementation of novel materials. Since 2003 he has been working in the area of embedded discrete components into laminates. He received his diploma in Plastic Engineering from the Montan University of Leoben, Austria.

Hannes Stahr studied electrical engineering at the Technical University Graz, were he received his Diplomengineer degree in 1988. He started as an electronic design engineer in Graz. In 1989 he joined the research and development activities of AT&S in Leoben Austria. At this time the R&D was founded in AT&S and he was instructed to implement the technology for impedance controlled boards. He was strongly involved in the development of the core technology a sequential multilayer technique and the HDI laser via technology to name the most important ones. Hannes Stahr is heading the Implementation of the R&D, the research and development branch of the AT&S group. Since May 2008 he is the consortium leader of the FP7 project Hermes. The Hermes consortium consisting of 10 European companies and AT&S driving the industrialisation of chip embedding in PWB forward.

Martin Biribauer was born in 1986, after graduating from an engineering college and a former international technical sales job joined AT&S 3 years ago. In the beginning he worked within the Solutions department, taking care of one-stop-shop solutions as Project Manager coordinating the whole supply chain from the first design idea to a finished board including SMT and box building. After that, now 2 years ago, he joined the ATS& Business Line Advanced packaging. He is now responsible as a Project Leader for customer project management for embedded boards of AT&S' global customer base, located in AT&S HQ in Leoben, Austria.

Mike Morianz studied Metallurgy at the Montanuniversity Leoben, where he received his Diploma degree in 2000. After that he joined the EPCOS OHG, working on ceramic semiconductors in the Process Engineering department. In 2004 he moved to the Piezo Technology business unit working for product development and production engineering for new ramp up of products.
Since 2006 he has been with AT&S, working in the Research and Development division. There he took the responsibility of the key development topic Embedding in the role as Programme Manager and transferred the Embedding Program to the Business line Advanced Packaging ramping up since 2010 in AT&S-Leoben. Since 2010 he is in the function as Operations Manager responsible for the department production, process development & engineering.
In addition he coordinates the Work Package 5 “Manufacturing Technology Integration of Embedding” of the EU-Project HERMES since 2008. In 2010 he received the best international paper award of the IPC APEX EXPO for authoring “Industrial PCB Development Using Passive & Active Discrete Chips Focused on Process and DfR”.

Nikolai Haslebner, Product Manager Business Line Advanced Packaging, AT&S AG. Born 1976, in Leoben/Austria, Graduated at the Technical University Graz, with Diploma for Technical Physics.
During the diploma thesis, he started to work at a start-up company which was engaged in the research of organic light emitting diodes. In 2004 he joined AT&S AG, in the research and development department. He started in the competence center for new technologies, where he was screening potential new technologies for printed wiring boards. One of these technologies, the integration of functionalities into printed wiring boards, quickly became the focus point of the development activities within AT&S. Currently he is product manager within the business line “Advanced Packaging” focused on embedding.

Abstract

The packaging market has gone through tremendous changes in the last years. Several different technologies have been created to fulfill the increased demands of the industry – e.g. downsized footprint while offering increased functionality.
Based on current packaging options (QFN, BGA,…) the embedding technology is aimed to drive the packaging possibilities to the next level and will compete against other new production methods (such as Fan-out WLP). Because of several advantages embedding has to offer, we are confident to establish this technology to be the main packaging option for the whole, quite demanding, industry.
As of these new industrial demands, embedding of discrete devices into PWBs has received a lot of attention lately for all kind of applications, ranging from traditional embedding in mobile phone engine boards to packaging solutions for RFID chips. Using embedding technology as a laminate based packaging solution is therefore a logical next step in packaging.
Environmental issues around the technology are becoming important and need to be properly managed to generate an error free path from the generation of the design data through the production line to the functional test. The standardization on the embedding technology has been started years ago and this year the activities for functional test have begun.
This presentation is going to outline the versatile AT&S ECP® technology process that can be used to serve all mentioned fields of applications. Starting from these process step, potential application are shown that highlight the capabilities of laminate based technologies, e.g. sensor packages, embedded passive devices, power modules,……
Furthermore the FP7 project HERMES (High density integration by Embedding chips for reduced size Modules and Electronic Systems) is presented. In the project, the industrialization of embedding technologies is one of the key targets, in addition to development targets, e.g. ultrafine line technology with 25μm line width and space for complex applications.

High-Speed Multi-Die DRAM Packages Fabricated Using Wire-Bond Infrastructure

Simon McElrea, President

Invensas

Joint paper Invensas, Tessera, NANIUM

Biography

Simon McElrea is president of Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq: TSRA). McElrea leads the innovation of novel technologies and intellectual property (IP) in areas such as advanced semiconductor packaging, 3-D systems, memory modules and other solutions that enable mobile, storage and consumer electronics devices.

Prior to Invensas, McElrea was vice president of Engineering at Tessera where he led the worldwide engineering and R&D organizations for the company’s Micro-electronics segment.

McElrea has more than 15 years of technical and executive management experience in semiconductor and package assembly businesses. Before joining Tessera, he held senior positions at Honeywell Electronic Materials, Amkor Technology, Vertical Circuits Inc. and Johnson Matthey PLC. A native of Northern Ireland, McElrea has lived in the U.S., Europe and Asia, working primarily on new technology ventures and high-volume manufacturing start-ups.

McElrea holds Bachelor’s and Master’s degrees, with honors, in Engineering Science from Oxford University. He has authored numerous patents in advanced electronics.

Richard Crisp, Principal Technologist and Senior Director, is responsible for advanced microelectronics packaging development, product strategy and market development at Tessera, Inc. where he joined in 2003. A long time CPU and memory circuit design engineer Richard has worked for Rambus Inc. MIPS Computer Systems, Intel Corp and Motorola Semiconductor where he began his career as a key circuit design engineer on the Motorola 68000 microprocessor. He has also served as the ISSCC Program Chair in 2000 previously having served as the Vice Chair, Memory Subcommittee Chair, and member of the Memory Subcommittee throughout the 1990s. He has over 20 US Patents and graduated from Texas A&M University in Electrical Engineering and has authored numerous technical publications.

Wael Zohni, Director of Memory Programs, is responsible for memory-related package development and engineering at Tessera, Inc. He previously worked at Tessera as a package development engineer from 1997-2006. He has 17 years experience in advanced packaging that includes work for Siliconix-Vishay and LSI Logic. He has worked at MetaRAM as a staff engineer before returning to Tessera in 2010. In his prior roles, Wael has worked on new product development as well as package design, qualification and manufacturing. He graduated as a Mechanical Engineer from Worcester Polytechnic Institute, Worcesterand holds several patents relating to package design and process.
Belgacem “Bel” Haba, Tessera Fellow and Chief Technology Officer, joined Tessera in 1996 and is responsible for overseeing next-generation research and development activities for Tessera, Inc. He is also a founder of SiliconPipe Inc., a start-up company based in California’s Silicon Valley. Prior to that, he worked at Rambus, NEC and IBM. Dr. Haba holds degrees from Stanford University in materials science and engineering. Dr. Haba holds 134 U.S. patents and has authored numerous technical publications.
Chung-Chuan “John” Tseng, Senior Engineer, Package Development, received his mechanical engineering degree from San Jose State University. He is responsible for physical design of advanced microelectronic packaging and process tooling. Mr. Tseng is also responsible for mechanical design for silent air cooling development at Tessera, Inc. where he joined in 2001. He has four US and foreign patents in semiconductor packaging and thermal management.
Rui Silva graduated in Electrical and Computer Engineering at the University Porto, Portugal. Subsequently, he worked in Siemens Semiconductores S.A in Test Operations department, as a DRAM Test Process Engineer. In 2005 Rui joined the Test Development group as Product Engineering Team Leader at Qimonda S.A., with the responsibility for defining the DRAM test plans, at first for DDR1,2 and later DDR3, GDDR3 as well as GDDR5. Since 2009 Rui hold the position of Staff Test Development Engineer at NANIUM S.A.
Luis Mendes, Senior R&D Integration Engineer: NANIUM S.A., has his degree in Materials Science and specialized in process microelectronics. He began his career at CEMOP (Micro and Optoelectronics Research Center) as an R&D Engineer, developing thin films produced by PECVD for sensors and PV applications. In 2000 he joined EPCOS (now KEMET) as a Process Engineer, developing the frontend and backend processes for SMT tantalum capacitors. In 2007, he joined Qimonda (now Nanium) as a R&D Integration Engineer for package development.
Nuno Vieira, Process Engineer: NANIUM S.A., holds degrees in Metallurgical and Materials Engineering from the University of Porto, Portugal. In 2004, he joined Infineon Technologies SA as a Quality Assurance Engineer for Assembly. In 2006, he became responsible for the Wire Bond Process in Qimonda SA. Since 2010 Nuno holds a position at NANIUM SA as a Process Engineer in Assembly Area, responsible for the Die Attach and Dispensing processes.
Carlos Delgado, Process Engineer: NANIUM S.A, is a graduate of Mechanical Engineering from the University of Minho, Portugal. He is currently responsible for the wire bond process at Nanium S.A. A position he has held for 6 years. Previously he was at Infineon Technologies S.A / Qimonda Portugal S.A Company.

Abstract

Signal integrity issues limit fan-out of memory modules to approximately one or two per channel in order to operate at 1333Mbits/sec/pin. Limiting the fan-out to a single DIMM, 1600Mbits/sec/pin operation can be attained.

There is a clear trade-off between memory capacity and clock frequency. It is beneficial to use high capacity modules to overcome this memory capacity limitation. Multi-die packages such as Dual Die Package (DDP) can be used to produce such high-capacity modules.

Unfortunately standard DDP DRAM devices operate at reduced clock rates versus single-die packaged DRAM for electrical and thermal reasons. Commonly-used structures feature DRAM die stacked atop each other with lengthy bond-wires used to connect to the package substrate.

The long bond-wires increase the inductance of the power leads causing an increase of the noise on the power rails of the DRAMs. This degrades the timing and voltage margin of the devices forcing them to operate at reduced frequency.

The inductance of the long bond-wires connecting the switching signals to the die causes impedance discontinuities that degrade the signal integrity of the high speed signals again limiting the operating frequency.

The stacking of the DRAM die, with significant plastic encapsulation atop the stack needed to protect the bond-wires of the upper die, increases the thermal impedance of the standard DDP aggravating thermal limits.

This work describes a new double die face-down wire-bonded package that solves all of the cited problems, yet is fabricated using existing high-volume wire-bond manufacturing infrastructure. The new package features partial overlap of the two die such that they are laterally displaced by a bit less than a half die width. There are two bonding windows in the substrate and the signal terminals are arranged in three groups rather than the pair used in standard DDP and Single Die Packages with their single bonding window.

The new package structure will be described in detail in the paper. Both simulated and measured performance data will also be presented. The measured data was obtained by building the new structure and control legs using live DRAM die from the same wafer lot. The control legs included both isolated die as well as conventional DDP top die configurations for comparison to standard devices.

First lot results using high speed 1 Gbit DDR3 live die with a x4 organization indicated a 68% improvement in final test yield to the 2133MT/s speed bin using the new structure versus conventional wire-bonded DDP controls. Additionally both die in the package have virtually identical electrical performance, effectively demonstrating single die speed in double die packaging. Thermal simulations reveal a 25% improvement in junction to case thermal impedance versus standard DDP packaging in a forced air server application environment.

Flip Chip Copper Pillar for Advanced CMOS : How to Anticipate a New Package Platform?

Jérôme Lopez and Richard Rembert
STMicroelectronics

Biography

Jerome Lopez received Engineer Diploma degree of PolyTech Grenoble (Joseph Fourier University) in materials engineering in 2000 including 2 internship period on microelectronic Packaging (Flip Chip and Reliability).
He started in 2000 in STMicroelectronics as BGA Laminate Substrate technology engineer following new IC substrate technology development for BGA/LGA package with suppliers and implementation on customer products from early R&D up to mass production.
In 2001 he was appointed BGA Substrate Design Leader having in charging substrate design and technology activities for all ST BGA products (Mobile (RF, connectivity, base band, analog, power management), Consumer (TV, DVD, Set-Top Box, Computer peripherals, printers, Automotive, Image sensor, Mems sensor …)) except high speed net-working devices. He was deeply involved for all those products in co-design, design rules, package definition with customer, new platform definition (Stack, SIP, POP, Sensors …), substrate new technology development, supplier audit, substrate technical cost reduction and supplier strategy.
He was awarded Expert in 2010.
Since 2008 he is deeply involved in new interconnect platform development - Flip Chip with Copper Pillar – and he is leading a corporate task force related to FC Cu Pillar development and implementation for all ST & STEricsson products using this technology since early 2011.

Abstract

This paper illustrates the need to bring closer the design and the semiconductor assembly & packaging communities.

Miniaturized, Higher performances, Cheaper and Reliable packages availability is crucial for accompany like STMicroelectronics. Indeed Package is becoming a key differentiator to be the first on the market, gain market share and get higher profitability especially in consumer markets.
Many new products require strongly improved electrical performances and miniaturization. Flip Chip is an obvious solution but :
- How to reach best system cost (package + bumping + silicon) ?
- What type of Flip Chip have to be used (solder, copper pillar, stud bump …) ?
- What is the impact on silicon design ?
- What is the impact on Co-Design methodologies ?
- What is the impact on reliability ?

We will present more in details the major steps we put in place in order to conclude on using Flip Chip Copper Pillar option for majority of our coming advanced CMOS products.
- Targets (cost, performance, rationalization …)
- Pro’s & Con’s
- Contributors / actors (from front-end technology to package assembly)
- Study conclusions

Through those data, we will summarize the main challenges to develop winning package solution for winning products at end customers with best synergy.

Key Technical Challenges for Silicon Interposer

Gilles Simon, Head of 3D Packaging Laboratory

CEA-LETI

Biography

Gilles Simon joined the CEA-Leti as a research engineer in 2010. He is currently in charge of the LP3D (3D Packaging Laboratory) within the Silicon Component Department. Prior to joining Leti, he spent 5 years developing analog testing for imaging products at Thomson TMS. Then 13 years in the packaging domain through Thomson Specific Component, Atmel Grenoble and e2v Semiconductors, as Packaging Group Manager.He developed specific processes mainly dedicated to high-end applications for imaging products as well as for data converters, micro-processors and Asics. Atmel period permitted also to work on volume production based on partnership with far-east assembly and test houses. Gilles Simon holds an engineering degree from the Ecole Nationale Supérieure de Physique de Grenoble – Signal Processing - after being graduated in Mechanics Design at Grenoble University. He is the author or co-author of about 5 patents in the packaging field, mostly dedicated to imaging and medical products housing.

Abstract

The silicon Interposer is still looking for its ‘blue ocean spot’. After reviewing the Si interposer positioning in the packaging world, a focus is made on the key technical challenges. If the manufacturing flow could be achieved, some remaining points have to be solved: the handling of thin wafers, including the bow monitoring, and the final assembly, including die / passives attach together with the 2nd level reliability. The presentation will overview the manufacturing flow of a complex interposer before addressing the back-end side.

Andreas Dill, CEO

Oerlikon Advanced Technologies

Biography

Born 1954, Swiss citizen. Since joining OC Oerlikon Balzers AG, Balzers, Principality of Liechtenstein in 1998, Andreas Dill has served in a succession of senior management positions, including General Manager Wafer Processing Europe and Vice President Global Strategic Business Units. In July 2007 Andreas Dill took over the responsibility for the Business Unit Systems (manufacturing equipment for Semiconductors, Optical Disc and Advanced Nanotechnology) at Oerlikon as a Senior Vice President and since 2010 he is the CEO of the segment Advanced Technologies. Prior to joining OC Oerlikon Balzers AG, he held several positions with the Swiss company Zevatech AG ranging from Project Manager to General Manager and, finally, Corporate Vice President of Advanced Technology. Andreas Dill holds a MEng in Electrical Engineering from the ETH Zurich, Switzerland (Swiss Federal Institute of Technology).

Challenges to Integrating Organic Materials into Advanced Packaging Applications – A PVD Tool Perspective

Simon McClatchie, Process Engineering Manager
Oerlikon Systems

co-authors: Albert Koller, Patrick Carazzetti, Paolo Montognoli, Thomas Ritzi, Bart Scholte van Mast (Oerlikon Systems)

Biography

Simon McClatchie has worked in the semiconductor industry for over 18 years specializing in various aspects of plasma processing (deposition and etch). He is currently Head of Process Engineering at Oerlikon Systems in Balzers. Prior to relocating to Oerlikon in Balzers, he held various technical management positions at other semiconductor equipment companies including Lam Research in California, and Trikon Technologies in the U.K. He holds a PhD from the University of Wales college of Cardiff, U.K.

Abstract

As the technology and materials used for advanced packaging applications continue to develop, the integration of materials other than Silicon Nitride present some additional challenges for the makers of High Vacuum (HV) deposition tools used for metallization. In particular, the use of spin-on organic materials, such as Polyimide (PI) or eWLB organic wafer material, presents multiple new challenges primarily due to these materials inherent outgassing properties. These organic materials readily absorb significantly more moisture when exposed to atmosphere than the previously used Silicon Nitride films, and this moisture can then outgas during subsequent vacuum and/or thermal processing. In addition these organic films, depending on how they are annealed, are also prone to outgas carbon containing materials during subsequent dry etching or deposition processes. These outgassed materials can cause device performance issues such as higher contact resistance, as well as adversely affecting wafer to wafer repeatability. In addition these evolved materials can also have a detrimental effect on equipment maintenance intervals and productivity.
For the HV deposition tool, the typical process sequence would involve degas, then etch, followed by the Titanium (Ti) and Copper (Cu) deposition steps. To successfully integrate these organic films it is important to further optimize each of the individual process steps to consider the following:

- Degas: remove as much of the “extra” outgassing material as possible from the wafer to prevent it from entering into the subsequent processing steps
- Etch (contact clean): Remove the native oxide from the pads and prevent re-oxidation or contamination (by newly introduced organic materials) of the now open contact pads
- Metallization: cover the open contact before any recontamination occurs and process in a regime which does not affect the underlying organic layers

Further optimization of the whole process sequence is then also necessary in order to preserve equipment maintenance intervals and keep productivity high.
This paper describes some of the challenges, for HV metallization tools, posed by the integration of organic films into advanced packaging applications, and also describes some of the methods used to address them.

Estimation and Localization of Bonding Defects in 3D-integrated Devices Using Scanning Acoustic Microscopy

Sebastian Brand, Department of Microelectronics and Microsystems
Fraunhofer IWM

Biography

1) Fraunhofer Institute for Mechanics of Materials IWM, Halle, Germany
2) PVA TePla Analytical Systems GmbH, Westhausen, Germany
3) AustiaMicroSystems, Unterpremstaetten, Austria
4) EVG, St. Florian am Inn, Austria

Abstract

In failure analysis often multiple analyses have to be applied to one and the same sample. In these cases the availability of methods operating non-destructively is of high interest in order to pursue the root-cause of the failure. Scanning acoustic microscopy enables a non-destructive illumination of optically non-transparent materials combined with a resolution up to the micrometer range. In 3D-integration devices commonly contain multiple bond interfaces that are potential candidates to be the cause of a failure when there is a defect in the adhesion condition. Common imaging applications in acoustic microscopy are capable of laterally localizing delaminated bond interfaces. However, due to the high acoustic velocity of silicon (approx. 8900 m/s), the corresponding pulse length and the imaging mechanism an assignment of a defect to a specific interface is extremely challenging. The current paper presents a method that applies specific signal analysis and processing algorithms that enables a synthetically achieved decrease of the acoustic pulse length in recorded ultrasonic echo signals of a stacked die device. This approach allowed an axial assignment of a delaminated region to a specific bond interface within the stack. It has also been applied to samples containing TSV structures for investigating the bonding conditions at the interface around the base of the TSV’s. The analysis tool developed performs deconvolution of the acoustic echo signals obtained at the interfaces between the stacked dies in order to separate these naturally overlapping pulses. Provided the dimensions of the internal structures are known and when applied comparatively using a reference sample the method developed here provides results with distinctly increased reliability in defect depth localization.

Thin die Stacking for Wide I/O Interface Memory-on-Logic

Thorsten Matthias, Director of Business Development and Paul Lindner
EV Group

Biography

Thorsten Matthias is director of business development at EV Group headquarters in St. Florian, Austria. In this role he is responsible for overseeing EVG’s worldwide business development.
Thorsten received his PhD in Technical Physics in 2002 from Vienna University of Technology. He started working at EV Group in October 2002.
In his current position he works in 3D integration, MEMS, photovoltaics, LED, and nanotechnology.

Abstract

Wide I/O interface memory-on-logic has the potential to be the killer application which could boost TSV and 3D integration into high volume manufacturing. The convergence of smart phone and media server requires DRAM bandwidth >12GB/s in order to allow streaming of 1080p HD videos onto large displays. Conventional memory-logic interfaces (“narrow I/O interface”) consume too much power at the I/Os and do not allow scaling to multiple hundreds or thousands of I/Os. Through silicon vias (TSV) enable a significant power reduction at the I/O, which enables wide I/O interfaces.
However, wide I/O interface memory-on-logic is one of the most challenging 3D applications for various reasons.
Form factor is crucial as mobile applications are the drivers. The individual memory layers will require a thickness of 30µm or even less. For temporary bonding and debonding very tight process tolerances are required. Any thickness variation of either carrier wafer or adhesive layer would result in significant thickness non-uniformities of the device wafer.
Multiple layers have to be stacked. Initial designs will probably require at least 4 layers with 8 layer stacks following very rapidly.
Memory stacking can be performed either as chip-to-wafer (C2W) or as wafer-to-wafer (W2W) process. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process. For ultra-thin wafers stacking before debonding might be necessary. For C2W this means dicing while the die is still on the carrier, which destroys the carrier and adds to the overall costs. W2W allows re-using the carrier wafer.
Cu-Cu bonding is the most promising process for memory stacking. Current activities are targeting a reduction of the bond temperature in order to reduce cycle time and cost of ownership, but also in order to facilitate permanent Cu-Cu bonding prior to debonding from the carrier.
This presentation will review state-of-the-art in thin die and thin wafer stacking for memory-on-logic applications.

EXHIBITOR PRESENTATIONS

Jan Vardaman, President

TechSearch International

Biography

Abstract

With the continued increase in the price of gold, the industry continues the transition to copper wire bonding. This presentation discusses the rising price of gold and its impact on the cost of packaging and assembly. Trends in the shift to copper wire bonding are discussed.

Pre-molded QFN Packages for RF & MEMS Applications

Andy Longford, Senior Consultant
Interplex Engineered Products

Biography

Abstract

The Air cavity package (ACP) is a widely used option for RF products, Hybrid circuit assemblies and optical/photonic devices. Typical standard ACP are metal cans and ceramic leadless chip carriers(LCC). Custom ACP are also provided by machined metal housings and LTCC options. The QFN outline is now widely available as a ceramic ACP and is being developed in lower cost plastic materials such as Liquid Crystal Polymers and Thermoset (Duraplast) premolded types. Unitil recently, 2 types of ACP QFN exist. A flat base variant (exclusive to RJR Polymers) which accepts a cavity lid, or ring-frame and flat lid cover, and a cavity wall package variant that can be filled (potted) or accept a lid. Interplex have developed a new option which has a low height cavity base and a cavity lid. This presentation will show why this package option is ideal for both MEMS and RF devices.

“More than Moore” – Heterogeneous Integration on Wafer Level, Enabled by Fan-out WLP

Steffen Kröhnert, Director Backend Technology

NANIUM

Biography

Dipl.-Ing. Steffen Kröhnert received his diploma degree in Electrical Engineering and Microsystem Technology at Technical University of Chemnitz, Germany, in 1997. In the same year he started his professional career as Development Engineer in the Corporate Package Assembly, Interconnect and Test Development Center for Semiconductors of Siemens AG in Regensburg, Germany. After carve out of the Semiconductors Business Unit to Infineon Technologies AG in 1999, he worked as Project Manager and moved to Infineon Dresden GmbH & Co. OHG in 2002 to support local setup of Package Development Department for Memory Products. He became R&D Area Manager Component Development and took over Technology Platform ownership for FBGA products. From 2006 he was working as Senior Manager in Qimonda Dresden GmbH & Co. OHG, the carve out of the Memory Products Business Unit of Infineon Technologies. Begin 2007 he was assigned to Qimonda Portugal S.A. to setup and lead Package Development team at volume production site. Since 2009 he is Director Backend Technology at NANIUM S.A. in Vila do Conde, Portugal. Steffen is author and co-author of 23 patent filings in the area of Packaging Technology. He is member of SEMI Europa Advanced Packaging Committee.

Abstract

The fan-out WLP Technology eWLB (embedded Wafer Level Ball Grid Array) is a recent Advanced Packaging technology that was initially developed by Infineon Technologies on 8” reconstituted wafer and has ramped-up to high volume production since 2009. In a joint development project between Infineon Technologies and NANIUM in 2010, this packaging technology was successfully extended to 12” reconstituted wafer for high volume production. The eWLB technology is gaining wider market acceptance, but has been restricted up to now to wireless applications leveraged by its advantages regarding performance, form factor and cost. Deploying its innumerous additional advantages, like design and integration flexibilities, thermal and electrical performance gain, reliability and robustness improvement, NANIUM has been engaged on recent R&D projects with different customers targeting the enabling of eWLB for other applications to enter new markets. Some of those projects reached already “Prototypes and Engineering Samples available” milestone. The presentation will give an overview about those new applications, where NANIUM sees eWLB gaining momentum.

Current Results and Future Approaches in Wafer-Level-Packaging at Fraunhofer ENAS

Frank Roscher, Research Associate,
Fraunhofer ENAS

Biography

The author is scientific staff member at the Fraunhofer ENAS at the department system packaging. He graduated from the Chemnitz University of Technology with a diploma degree in Micro-Production-Technologies. As a part of the Gessner group he spent 6 months in Sendai, Japan for research on novel materials for system packaging solutions. His current research deals with interposer technologies and low temperature bonding solutions.

Abstract

Wafer bonding is a packaging technology on wafer-level for the fabrication of micro electro mechanical systems (MEMS) as well as for microelectronics, nano electro mechanical systems and optoelctronics. The packaging ensures electrical contact or insulation, mechanically stable and hermetically sealed encapsulation. Beside common used bonding technologies like anodic bonding, adhesive bonding, glas frit bonding, eutectic bonding, direct bonding and thermo compression bonding there is a strong need for new technologies and materials to lower the process temperatures during packaging to enable new sensor and actor concepts as well as new products i.e. for medical applications, automotive and consumer markets. The development of 3D vertical integration with photostructurable glass will be discussed as well as low temperature bonding by using silver nanoparticles and reactive multilayer systems.

Enabling Processes for 3D Interposer
Thorsten Matthias, Director of Business Development and Paul Lindner
EV Group

Biography

Abstract

Interposers are becoming more and more important for advanced packaging as they provide unique advantages in terms of interconnect speed, fan out connections, heat spreading and integrated passives. Interposers are being used for a wide variety of devices already in the field of MEMS, RF and LED packaging. However, the main drivers for interposer technology are memory and memory-on-logic applications.

This presentation will review enabling process technology for the manufacturing of silicon interposers. The Nanospray® process allows creating TSV sidewall passivations with organic dielectrics, which have a thickness of multiple micrometers. This results in superior electrical performance. Thin wafer handling is a key technology as interposers have only a thickness of 50 to 100 micrometer. Advanced chip-to-wafer bonding (AC2W) allows reducing the process time for chip stacking as it enables simultaneous bonding of all dies.