The author started his career as a Product and Test Engineer for ASIC products more than 20 years ago at VLSI Technology. Since then, he has been holding various positions both as engineer and manager in the DFT and ATE arena, working in Germany , the United States  and in France. He is currently working as a Member of the Technical Staff for ST-Ericsson in Sophia-Antipolis focusing on test development solutions for Smartphone and Tablet application processors.

This presentation will address the implementation of a concurrent test scenario on a highly integrated system-on-chip 3G base band processor with many multimedia features as well as a complete audio system and baseband to RF interfaces.  This device has been designed in a 65nm CMOS technology,  consisting of  approximately  60 million transistors and 628  pads .
The fact that a significant part of the design consists of analog blocks which contribute over proportionally to the overall test time, it was decided from the beginning of the project to pursue the possibility of testing several independent system blocks concurrently.
The presentation will start with an overview of the different possibilities of concurrent test implementations. It will compare the approach of testing two (or more) independent dies in one package concurrently versus a testing several internal sub-systems inside one die concurrently. It will further outline the requirements necessary of the Design for Test implementation in order to allow the execution of tests concurrently.
Another chapter will focus on the test development flow. This will describe on how to select the tests to be executed concurrently as well as the subject of test time balancing. Due to the complexity, the test program development was split over various test departments. The novelty of the approach required further the cooperation with our Automated Test Equipment supplier (VERIGY) in order to benefit from their expertise and technology.
Since this project is already industrialized the author will further reflect on the challenges encountered while introducing the device to mass production in respect to concurrent test.
In addition to concurrent test the test program and hardware was designed in such a way that two devices are tested in parallel therefore further reducing test time and  optimizing the existing tester resources as compromise to added complexity.
The fact that the ATE vendors will need to implement tools in their software tools in order to facilitate and ease the development flow will be described based on the experiences of the author.
As a summary the benefits like the reduced test time as well as limiting factors will be discussed like tests that cannot be executed concurrently like functional tests or DC test using boundary scan tests. 

 

Fritz Köhldorfer has graduated in Biomedical Engineering at the Technical University of Graz. After that, he was employed at the automotive branch as a Real Time Software Engineer. Since 1998 he is employed with austramicrosystems as a Test Engineer. As a Test Engineer, he is responsible for developing test programs, developing assist systems for the test program development, developing and designing software for the test production environment.

After graduating an electronic and RF engineering high school in Grenoble (France), Francois has been working for several companies. He joined NXP semiconductors (formerly Philips) in 1997. As a Principal Test Engineer, mainly focused on improving current industrial test processes and defining the test and DfT strategy for new products.

In the consumer market, the semiconductor companies have to consider the cost as a killer factor, while providing high levels of quality. In order to improve margins (and keep them positive when price erosion arrives!), those companies are constantly looking for methods to decrease the production test costs. The most common techniques include multisite testing, the reduction of the industrial test time and the transfer to cheap tester platform.
Applying such techniques to complex RF products like Silicon Tuners is very challenging because those ICs are demanding in terms of RF & mixed-signal resources and test coverage. A Comparison of several possible solutions will be presented including: using tester options, implementing hardware on the test board and adding additional feature in the IC for test purpose (Design for Test). Indeed DfT and BIST solutions help 1) move toward a low cost simple tester by integrating the required source or measure features in the device, 2) increase the multisite factor as less tester resources are needed and 3) reduce the test time thanks to fast and dedicated embedded instruments.
In order to quickly deploy such low cost test solutions to several products and ease the transfer from higher cost tester platforms, specific SW techniques are used. Structured high-level programming and product-oriented coding style allow faster development time and quick platform transfer, even if the tester language (visual basic, C++ …) is not the same when changing from one equipment supplier to another.
The presentation content is based on the industrial development of an octal site wafer test for a Silicon Tuner currently running in production.

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Thomas Herrmann is MTS Product Engineer at GLOBALFOUNDRIES Yield Analysis Systems team focusing on Yield Learning through Scan Diagnosis. Previously, at AMD, Thomas was a member of the Dresden Design Center taking care of DFT, Test and Product Engineering as well as yield and defect analysis of a number of complex digital products. He earned his MS in computer science from the University at Jena, Germany.

Geir Eide is the product marketing manager for Silicon Learning Products in the Silicon Test Solutions group at Mentor Graphics. His current focus is on diagnosis, yield analysis, and silicon debug. Previously, Eide held positions related to design-for-test, semiconductor test, and debug, Teseda Corporation and Magma Design Automation.  He earned a BS and an MS in Electrical and Computer Engineering from the University of California at Santa Barbara, and has an engineering degree from Kongsberg College of Engineering, Norway.

Chris Schuermyer is the Product Lead for the emerging area of Diagnosis-Driven Yield Analysis in the Silicon Test Solutions group at Mentor Graphics.  His primary focus is on designing solutions for exploiting design and test data in order to provide root cause identification of yield limiters in the advanced process nodes.  Previously, at LSI Logic, Chris was a member of the Advanced Defect Screening group, chartered with using test data to improve product quality and product yield.  He earned his MS degree in Electrical and Computer Engineering from Portland State University in 2005 and his B.S. degrees in both Physics and Electrical Engineering in 2002. 

Sagar A. Kekare holds a Masters degree in Materials Science and Engineering from University of Texas at Arlington. He is currently Group Manager of Product Marketing at Synopsys. He is responsible for the Yield Management group of products. Prior to joining Synopsys, he was a Senior Yield Management Consultant for KLA-Tencor and a Process Integration Team Leader for Rockwell / Conexant Systems.

Vincenzo Tancorre received a BS in Electronic Engineering from Politecnico’ di Bari in 2000. He works as Yield Enhancement Engineer at STMicroelectronics. His major responsibilities include parametric correlation and statistical data analysis to support yield enhancement of Automotive SoC devices during the ramp up phase of new technologies.
Christophe Suzor holds a degree in Chemical Engineering from University of Melbourne, Australia, 1992. He has worked at Tokyo Electron, Philips Semiconductors, Electroglas, HPL, and Synopsys. He uses his strong manufacturing and test background to provide yield analysis expertise as member of Yield Management R&D team at Synopsys.

Prevalence of subtle systematic failure mechanisms in nanometer nodes has reduced the effectiveness of in-line defect capture operations. Wafer sort test has been increasingly moving away from a simple pass/fail gauge; it’s now expected for it to provide clues about the defect types, and drive the understanding of failure mechanisms. For the modern System-on-Chip devices a defect could occur in any of the Logic, Memory or the Analog portions of the circuit. Structural testing and Memory Bitmapping approaches assist in locating the systematic defects. In either case the sort test is required to apply a comprehensive set of test patterns, collect the identity of the failing cycles and provide them back to a simulation and heuristics based diagnostics engine. The diagnostics localizes the defect in the chip. At this time the product engineers may send this defect location to Physical Failure Analysis. But that is a lengthy step and it still tells the engineer only about why that one device failed.
In order for wafer sort test to have a significant positive impact on the time-to-volume for the device, the diagnostics data needs to be collected over multiple failing devices and analyzed for statistical signatures of systematic failure locations. These signatures must then be associated with appropriate design elements through correlation across various design data. The design elements that correlate to strong statistical signatures need to be normalized for their native failure rate against the frequency of their usage in the device design. Finally these design element locations need to be offered for further investigation after prioritization based on their yield impact. This way the engineers can discover the most dominant systematic failure mechanisms and improve the yield with best possible increments.
This approach of volume diagnostics is ideal for early phase of new product yield ramp. However it does mandate incrementally higher test resources for applying the comprehensive tests, computational resources for performing the diagnostics and volume diagnostics, and the operational cost of having the production batches at the test floor till all the analysis is done. This is not the most realistic approach for high volume production. Hence, the early phase of yield ramp needs to also focus on how the knowledge gathered can be applied towards reducing this overhead during volume production. Characterizing the test response of the new device across all the Process, Voltage, and Temperature corners allows for effective test time reduction while maintaining confidence in the amenability of the test results to diagnostics. Additionally, understanding the excursion frequency of dominant failure mechanisms drives the creation of a representative sample plan for tester data-logging and diagnostics of production failures. Correlation of diagnosed systematic failures to in-line defect data, functional and parametric test data provides a path to quickly detect a yield event that warrants data-logging and diagnostics based on functional test results.
This paper describes a design-centric yield analysis system that enables its users to tackle all of the above activities in a single yield framework. We will provide a summary of the in-depth analysis performed during early phase of yield ramp. Next we will present the strategies used to employ the volume diagnostics solution in mature production. Finally we will propose an innovative approach that uses advanced data-mining techniques to identify signatures in functional and parametric data which can act as early warning of an excursion of a systematic failure mechanism, and allows for rapid tuning of production test, data-logging and diagnostics sample plan to capture such excursions with high confidence. 

Thomas Thärigen studied physics at the University of Leipzig and graduated 2001 with a Ph.D. (Dr.rer.nat.) in solid state physics. In the same year he joined the SUSS MicroTec Test Systems GmbH as Product Manager for an atomic force microscopy based multi-tip probing tool. In 2005 his responsibility enlarged to the complete product line of probe systems for Failure Analysis Applications. In this positions he earned a lot of knowledge of probing needs and solutions for complex semiconductor devices, especially probing on (sub)micron non-standard pad structures as it is common for failure analysis approaches. He is an active member of the German ITG 8.5.1. group “failure localization in electronic devices” and holds five patents. With the emerging of the 3D stacking technologies he was taking over in 2008 the responsibility for the SUSS product line of test equipment for 3D wafer level semiconductor test. Since the acquisition of SUSS Microtec by Cascade Microtech in 2010 he works as Product Marketing Manager for Entry level, Failure Analysis and Packaging Test solutions which includes 3D TSV test. By closely watching the 3D stacking market he acquired in-depth knowledge about the 3D test challenges.

Eric W. Strid is cofounder and Chief Technical Officer of Cascade Microtech, Inc., a company which develops, manufactures, and markets high-performance wafer probes, sockets, and probing systems worldwide.  Eric created the first 18-, 26-, and 50-GHz wafer probes, holds over a dozen patents, and has published numerous technical papers.  In 1987 he received the IEEE ARFTG Automated Measurements Technology Award, and in 1991 he received the IEEE MTT Society’s Microwave Applications Award. In 2002 he served as Technical Program Chair for the IEEE International Microwave Symposium.   Prior to Cascade, he designed gallium arsenide integrated circuits and microwave integrated circuits at Triquint Semiconductor, Tektronix, and Farinon Electric.  He holds the SBEE degree from MIT (1974) and MSEE from UC Berkeley (1975). 

Recent advances in semiconductor processing technology enable the manufacturing of integrated circuits with Through-Silicon Vias (TSVs). A TSV is a conducting nail that provides an electrical connection though the substrate of a thinned-down silicon wafer to its back-side. TSVs are used to create vertical inter-die connections that provide higher density and performance at lower power dissipation than conventional technologies such as wire-bonding. TSVs are used both in three-dimensional stacked ICs (3D-SICs), as well as in so-called 2.5D-SICs. 3D-SICs are vertical stacks of active dies that offer a small footprint and form-factor, which is particularly attractive for hand-held and portable applications. In 2.5D-SICs, multiple active dies are placed side-by-side on top of and interconnected through a passive silicon interposer base; this interposer typically contains TSVs to connect to external I/Os in the package substrate. 2.5D-SICs do not necessarily reduce the footprint, but offer better cooling options for high-performance compute and communication applications.

The prevalent bonding approach for both 2.5D-SICs and 3D-SICs is by means of small micro-bumps. Currently, these micro-bumps come at 25m diameter and 40m pitch. Micro-bump dimensions are subject to further down-scaling, as they, and not the TSVs, are currently the bottleneck in achieving higher interconnect densities. Typical micro-bump metallurgies include copper and tin.

Where wafer tests typically pay off for conventional 2D chips, this is all the more so for 2.5D- and 3D-SICs, were wafer testing cannot only prevent packaging costs, but also avoid stacking of bad dies on good stacks or good dies on bad stacks. So in order to achieve acceptable compound stack yields, there is a need to perform pre-bond testing, i.e., testing before stacking. The non-bottom dies in a stack do not have functional I/Os other than these micro-bumps, if which size and pitch are too small for conventional probe technologies. Hence, the current state-of-the-art is that companies add large dedicated probe pads on their non-bottom dies, serving no other purpose than to provide pre-bond probe access. This not only requires significant additional design efforts, but also increases manufacturing cost by adding additional process steps. Furthermore, the potential number of the dedicated probe pads is limited due to associated area cost.

In a joint research effort between Cascade Microtech and IMEC, we try to eliminate the need for these additional pre-bond probe pads, by enabling probing directly on the micro-bumps themselves. Providing proper electrical contact at fine-pitch micro-bumps with new metallurgies for realistic array sizes and with limited probe damage as to not impair downstream bonding, requires new concepts in probe cards and probe stations alike. We will show a promising approach and present recent results of our joint efforts.

Luc Van Cauwenberghe is currently managing the Pilot Line of ON Semiconductor in Oudenaarde (Belgium). Luc graduated from KAHO Sint-Lieven, Gent (Belgium), in 1997 with an industrial engineering degree in electronics. He started his career in 1997 as an equipment engineer. In his current position he is responsible for the engineering team that develops new test processes and hardware for Wafer Probe and Final Test related to new product developments in Oudenaarde.

Frank De Ruyck is currently working as an equipment engineer in the Pilot Line of ON Semiconductor in Oudenaarde (Belgium). Frank has a technical degree in electronics, specialized in process control from the Technical Institute Sint-Amandus, Gavere (Belgium). Frank has more than 20 years experience with semiconductor test and mechanical finishing equipment. In his current role as equipment engineer he is responsible for the development of new test processes and hardware for wafer probe. 

Wim Dobbelaere is the Director of Test & Product Engineering for the APG Automotive Mixed Signal business unit of ON Semiconductor. He received an M.S. degree in Electrical Engineering from the University of Illinois at Urbana-Champaign, USA and a Ph.D. in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium (KUL) doing  his research at the Inter University Micro-Electronics Center (IMEC). Wim has more than 20 years of semiconductor experience in various jobs in Waferfab, Product Engineering, Test operations and Test Development.

Riccardo Vettori is currently working as R&D Engineer for Cantilever Probe Card of Technoprobe in Cernusco Lombardone (Italy). Riccardo graduated from Politecnico in Milan (Italy), in 2003 with a biomedical engineering degree. After few years in the biomedical ambient where he developed new surgical micro equipments, he started to work in Technoprobe in 2005. In his current position he is responsible for the development of new cantilever probe cards and he originated patents for Technoprobe.

Marco Di Egidio works in the semiconductor industry since 1988 as Process Engineer in R&D and manufacturing. His mains job experiences are GaAs crystal growth by MOCVD and semiconductor electrical characterization (Alcatel Italy); he was in charge for dielectric thin film deposition and optical coatings processes for laser pumps devices (Pirelli Optical Technologies). He joined Technoprobe in 2004 and he is in the R&D process engineering team working on Cantilever Probe Cards.

The usage of advanced integrated circuits in the automotive industry has increased significantly over the last few years.  Most of these highly integrated ICs have to operate reliably in extreme temperature conditions and need to be able to handle high power and voltage requirements. In order to be able to achieve the required quality level multiple test insertions are required at extreme temperatures at package test and more recently also at wafer probe.
Today’s challenges for wafer probing of automotive integrated circuits are related to: limitations in the disturbed bond pad area , limitations in probe depth, limitations in the touch count and multiple wafer probe insertions at extreme test temperatures (-45°C up to 175°C).
In this paper ON Semiconductor and Technoprobe will share some of the lessons learned during the development of leading edge wafer probe solutions that comply with the automotive requirements. Both cantilever style and vertical style wafer probe solutions are addressed. We will first review the bond pad disturbance (area and depth) of existing probe card solutions and the impact of operating at extreme temperatures. Next, we will share the performance of novel probe card technologies that are patented by ON Semiconductor and Technoprobe.
The actual implemented probe solutions not only fulfill the automotive requirements, they also enable multisite testing of highly integrated IC’s in combination with advanced Automated Test Equipments.

After having fulfilled his militarily duties, Rene Segers started his professional career at Philips Research, back in 1976. Already then the focus was on DfT and on testing of electronic circuitry. After about 7 years at Research, he moved to various management positions in many Product Divisions of Philips including like Consumer Electronics, the Centre for Manufacturing Technology and Philips Semiconductors which later became NXP. Technically, the focus broadened from DfT towards DfX and supply chain management. He left NXP in 2009 and is since then active as an independent consultant.

 

Michel Villemain has more than 20 years of experience in the semiconductor back-end business. He is currently CEO of Presto Engineering (www.presto-eng.com), a company he founded in 2006.

Michel has been Vice President Marketing at FEI, and General Manager of the CD-SEM Business Unit at KLA-Tencor. Michel started his career with Schlumberger (later NPTest), where he served in various technical and managerial capacities over 19 years, in Europe, Texas and California. He has served as General Manager for Schlumberger ATE Europe, Vice President Marketing of the Test Division, and for five years General Manager of the Probe Systems (IDS) Division.

Michel graduated from Ecole Polytechnique in France, and holds a Ph.D. in Computer Science from Orsay University.

 

 

Stéphane IUNG began his carrier in the semiconductor industry 15 years ago after graduating from Ecole Supérieure d’Electricité (Paris, France).
He firstly joined IBM Semiconductors as Yield and Characterization Engineer, focusing on DRAM products.
Then he moved to STMicroelectronics, Grenoble, taking the role of Test and Product Engineering Team Manager in charge of high volume products in advanced technologies for Set-Top-Boxes market.
He recently joined QUALTERA as Europe Field Operation Director. QUALTERA is a French-based start-up company developing a Decision Support System for the semiconductor test industry (IDMs, fabless, test houses, foundries). It provides instant access to yield data, reports and draw meaningful conclusions to lead the semiconductor tests engineers, managers and executives to the right conclusion.

Toni Dirscherl holds a degree as Electronic Engineer from the University of Applied Science in Munich, Germany and joined SZ Testsysteme as Development Engineer for Analog DSP frontends in 1997. After serving 3 year as Senior Application Engineer for SZ Inc and Credence in San Jose/California from 2001 to 2003, Toni Dirscherl took over the position as Product Marketing Engineer for Credence-SZ GmbH. Since the acquisition of Credence-SZ by Advantest Europe in 2008, Toni Dirscherl acts as the Product Manager for Advantest’s Integrated Power Solution. He has published numerous articles.

 

 

Currently responsible for the Test activites at Nanium S.A.
Member of the SEMI European Manufacturing Test Conference Committee.

Joined Siemens Semicondutores S.A. in 1997 integrating the initial project team for factory start up and ramp. Held several management functions in the areas of Failure Analysis, Yield Enhancement, Operations, Product Engineering and Test Development at Siemens / Infineon / Qimonda / Nanium.
Previously, a researcher during 2 years, at INESC Lisbon - Magnetic Recording group working on the read/write thin film heads and its applications.
Holds an Engineering Degree in Physics Engineering by Instituto Superior Técnico (Lisbon) and an MBA in General Management from EGP – UBPS.

 

Coming from an IDM (Qimonda AG, a DRAM supplier) with the challenge to reorient its business and broaden its Test Services Nanium S.A. is a result of the semiconductor industry consolidation.

Offering competitive Test services to a broader range of products, dealing with the “More Than Moore” trend are some examples. Reutilizing existing equipment, minimizing new investment has been a key point to address the business opportunities. This presentation will give an overview of several test projects in the areas of SiP’s, MCP and eWLB.

 

 

 

David Brown is a Vice President at Aeroflex responsible for sales and service of Aeroflex test equipment in the EMEA (Europe Middle East and Africa) sector.  He has been in this position for 5 years.   David graduated from Nottingham University in the UK and subsequently worked at LTX Corporation for over 20 years where he worked in a number of engineering, marketing and sales positions in Europe and Asia.

The semiconductor world is under ever increasing cost pressure due to the pressures of the new mobile consumers and ever reducing pricing for data across a range of applications.  This price pressure puts relentless demand on semiconductor companies to get more efficient at moving devices from engineering to production and for achieving the lowest possible manufacturing test cost for RF, mixed signal and digital chips.
Engineering lab solutions are not suitable for production and production solutions are too expensive for the lab.  A new way to build semiconductor test systems based on new standards available in the test and measurement industry offers a way forward.   Standards such as PXI, ATCA, AXIe and Visual Studio C programming allows the design of a modular test system that can be affordable for engineering and allow engineering test investment to be re-used in production test.  These new technologies are brought to life in the AX-Series systems recently introduced by Aeroflex.