Abstracts and Biographies

• New Repeatability and Reproducibility Methodology for Semiconductor Testing
• High Speed Interface Testing - Implementing low cost reusable test solution through DFT using versatile ATE
• Boosting Test Execution by Turning Parametrical Into Functional Tests
• Lessons Learned in Deploying Part Average Testing in a Production Environment
• Efficiency Improvements in Parametric Test Using Adaptive and Parallel Test Concepts
• Panel introductory presentation: Title: XATF – eXtendible Adaptive Test Format - A Next Generation Test Data Feedback Format as an Enabler for Adaptive Test
• Adaptive Testing in Electronics Manufacturing Services – A Case Study
• The Test Program Factory – Automatic Generation of Platform Independent Test Programs
• Automated Failure Analysis Flow on BIST supported Memory Devices
• IC Yield, Reliability and Prognostics Using Nanoscale Test Structures
• Panel Discussion: “Can we make our business more efficient by focusing, outsourcing and sharing key resources?”
• Panel introductory presentation: Labless Model Accelerated Adoption In Europe

SESSION 1: Efficiency and Effectivity Improvements in Test Operations

New Repeatability and Reproducibility Methodology for Semiconductor Testing

Abstract

In a measurement process, Quality is achieved only if “good measurements” are performed. Values must remain unchanged within the same gauging set (repeatability) and in time (reproducibility). In the semiconductor testing arena, the current Repeatability and Reproducibility (R&R) methodology is based on the well known ANalysis Of VAriance (ANOVA) statistical technique. It is applied to the relevant parts of the measurement system, where the first element is Automatic Test Equipment (ATE) and the last is the Device Under Test (DUT) or a sample representing it. In this paper, we present a new method, based again on ANOVA, where ATE is addressed separately from the rest of the chain and “aligned” independently from the DUT and related parts. We achieve this through a platform-oriented tool able to stimulate each critical ATE resource in a relatively short time. All DUT-dependant parts, such as load boards, probe cards, etc., are “aligned” separately through standard correlation methodologies. Consequently, each new DUT can be easily released to production through a very fast correlation procedure. We demonstrate the advantages of this new approach vs the standard one, in terms of test quality, reliability, efficiency and reduced impact on manufacturing environment.

Biographies

High Speed Interface Testing - Implementing low cost reusable test solution through DFT using versatile ATE

Abstract

The Mobile market is driving “time to market” reduction and continuous price erosion by defining standard interfaces which allow faster and easier system integration together with improved performance and complexity. 
When it comes to test these new interfaces, the classical solution is to use high performance dedicated board on test equipment developed by test equipment supplier and to duplicate it on production test cells. Using this approach, the cost of test becomes very high and the tester configuration starts to be difficult to be managed in a flexible way.
This paper relates how we have leveraged on both DFT and versatile test equipment to develop a very low cost and plug-and-play test solution for MIPI D-Phy multi-lane interface (up to1.6Gbps).
After a step of extensive characterization and DFT validation conducted on a high performance tester set-up, we were able to migrate on standard production (sub-set) platforms at an optimized cost of test with excellent test coverage in line with our customer expectations. 
Finally, this document shows how the re-usable flow will then drastically improve the test elaboration time, thus the time to market as well as the global cost of development of future devices. 

Biography

Boosting Test Execution by Turning Parametrical Into Functional Tests

Abstract

One of the key parameters determining the overall test-cost is the electrical test-time of an integrated circuit. The main contributors at this are DC- and parametrical tests like e.g. voltage levels or timing values. Even though big progress has been made in the recent years by introduction of techniques like stored tester states or concurrent test, parametrical solutions still consume considerably more test-time compared to functional tests.
The presentation describes various examples of converting parametrical into functional tests independent of the available tester platform. It starts with tools that generate an overview of the execution time per test. Then the conversion of a parametric continuity test into a fast functional test with open and short capability and the modification of measurements like output levels or termination resistors into a simple test pattern execution are explained. Furthermore sophisticated approaches that combine parametrical and functional features for the test of output timing skew or propagation delays are presented. The necessary modifications for the level and timing setups and for the appropriate test pattern are described and the necessary pre-requisites for the test-system in focus are discussed before such a conversion can be started.
The presentation is accompanied by a case study of a registered buffer for Double Data Rate 3 (DDR3) memories where a reduction of the electrical test-time by more than 50% was achieved through the application of the above principles.

Biography

SESSION 2: Adaptive Test Experiences and Its Future

Lessons Learned in Deploying Part Average Testing in a Production Environment

Abstract

Over the past few years Part Average Testing (PAT) has been adopted by Analog Devices and a number of other semiconductor companies, primarily to help them meet the stringent reliability requirements of the automotive industry. While the Automotive Electronics Council (AEC) guidelines clearly lay out the basic principles for PAT, there is still a lot left to the interpretation of the device manufacturer. Questions such as which tests to apply to PAT, which binning rules to use, and when is the test process stable enough for PAT binning- are all up to the manufacturer’s discretion. One of the major issues ADI and other cost-conscious suppliers face is how to make the tradeoff between potential improvements in defects per million (dpm) and increased yield loss. Another significant challenge is how to integrate PAT to be a seamless part of the manufacturing process.
In this paper ADI and Galaxy will share some of the lessons learned in PAT deployments over the past 3 years and how a closed-loop process is the best way to make the optimum tradeoff between dpm and yield, and make PAT and related techniques cost-effective. It begins with up-front characterization to predict yield impact, adapts the rules to each lot as necessary, and finally monitors PAT yield loss to alert manufacturing when there are any significant excursions. In addition, we will discuss the implications of PAT on the workflow, and how PAT has been successfully integrated into MES environments.

Biographies

Efficiency Improvements in Parametric Test Using Adaptive and Parallel Test Concepts

Abstract

An effective way to reduce test time and therefore cycle time and capital expenditures at parametric test and to foster the goal to accelerate growth is the creative combination of adaptive and parallel test concept. Adaptive test provides the possibility to test MON (Monitor) / WAS (Wafer Acceptance Specification) / REL (Reliability) / WLR (Wafer Level Reliability) parameter with individual and flexible test coverage. On basis of some already production released processes the authors will show the effective combination of adaptive and parallel test regarding test time reduction and how flow-/component dependant testing is established by maintaining only one master test program. With the automatic forced wafer mapping, one of the key features of adaptive test, remarkable test time savings wer*e achieved which resulted in a significant number of tester saving.

Biographies

Panel Discussion: “The Future of Adaptive Test: Where and How to Adapt?”

Panel introductory presentation: Title: XATF – eXtendible Adaptive Test Format - A Next Generation Test Data Feedback Format as an Enabler for Adaptive Test

Abstract

Semiconductor test is challenged by at least three developments: (1) an ever increasing cost pressure, caused by rapidly decreasing silicon cost, which makes test consume an increasing fraction of the overall bill of material, (2) higher demands on quality of outgoing parts, driven by the increased pervasiveness of semiconductors in our daily lives and (3) an increased supply chain complexity driven by new business models and higher levels of final product integration. Adaptive test has emerged as a very promising means of addressing the drive for reduced test cost and increased quality. However, it requires having the right data at the right place at the right time, causing a drastic increase in data volume. At the same time, this data has to flow smoothly along the ever more complex supply chain. Hence it is high time to consider how to standardize the data flows to guarantee their reliability and at the same time enable extendibility in the underlying data format, so that new and emerging concepts – we have by far not yet seen all imaginable algorithms in and applications of adaptive test – can be implemented in a consistent manner at minimal incremental cost.
XATF – what and why? The current test data feedback de-facto standard, STDF v4, was conceived in an age where computer memory was expensive and the need for comprehensive test data collection and supply chain integration was minimal.
XATF on the other hand is designed from the ground up with the following considerations in mind: The potential scope is all technical data to and from test stages along a semiconductor supply chain, encompassing fab data, probe data, burn-in, final test, card and system test. Chunks of data can be added or removed (docked/undocked) along the manufacturing chain as fits the specific needs.
An XML based framework is the essential enabler for this wide scope: The underlying schema lends itself to easy extendibility. At the same time, it allows one to tap into the huge XML based software eco system to manage the data flows along the supply chain.
The bulk data, such as device level parametric data, which cannot be effectively encoded in XML is stored in an SQL database, which itself is contained in the XML framework. This brings the power of a relational database system both to the tester – where advanced adaptive test schemes can make use of it – as well as to the product engineers workbench.
To facilitate the introduction of XATF, the migration path from STDF based environments must be carefully considered and a loss-less conversion of STDF into XATF must be guaranteed.

Biography

SESSION 3: to be determined

Adaptive Testing in Electronics Manufacturing Services – A Case Study

Abstract

This presentation describes a case study on Test Time Reduction (TTR) in Board Testing. The underlying investigation has been executed in collaboration with the Althofen Site of Flextronics International. Employing genuine and unique test optimisation algorithms created by optimiSE, we investigate the TTR potential in a high-volume Printed Circuit Board (PCB) production line. Similar to semiconductor test, the challenge in a high-volume PCB line is the ever- rising cost of test, combined with increasingly demanding quality request of the (end-) customers.
There are several test stages to pass for a PCB, displaying rather different optimisation potentials (ordered sequentially):
(i) Optical Inspection – main problems are pseudo-flaws
(ii) In-Circuit Test (ICT) – standardised procedures, cost-intensive adapters
(iii) Functional Test (FT) – product-specific tests, long test times
(iv) Final Check – few, product-individual tests, the safety net w.r.t TTR
From a test programme and data analysis point-of-view, especially stage (iii) and, with respect to test correlations, stages (ii) and (iii) combined, are candidates for TTR: (i) TTR Potential in Functional Test: A standard test programme contains between 80 and 200 tests, compiled in test groups, which are separated by system waits. Technical options like minimizing the latter are usually the first step in TTR. After this, however, a detailed test stability analysis based on a large set of PCB measurements has to follow to highlight “inner” dependencies of tests. In the particular study underlying this report, a numerical reduction potential (determined purely from test information content) of almost 20% of the total test time is detected. Taking into account technical limitations as well as customer requests, an effective TTR of app. 12% is achieved on the line. (ii) PCB’s are traceable by serial numbers, permitting a “ICT + FT” analysis: The IC-Test per se does not offer a significant reduction potential, since, once the (expensive) test adapter is built, the test programme is basically “frozen”. Its importance, however, lies in a possible test coverage overlap with the FT. Indeed, several statistically significant correlations between ICT- and FT test groups are detected in the present study. This information further enhances the described TTR potential in FT. Finally, let us mention that a first version of an Adaptive Test Controller has been implemented for “experimental runs” on a Functional Tester at Flextronics International, Althofen Site. Evidently, before implementing the Controller in the production line, simulations such as the present case study are indispensable.

Biography

The Test Program Factory – Automatic Generation of Platform Independent Test Programs

Abstract

The task of developing and maintaining test programs for memory products is becoming increasingly complex. There is a constant development of new products in order to provide a better fit to specific customer features, quality and reliability needs.
In addition, test floors flexibility requires a product to run on more than one type of a tester, thus requiring multiple sets of the same test program to be developed and maintained. All the above results in incremental costs of labor, longer new products development time, duplicate work for test programs modification, and long test Program conversion time from one tester platform to another.
To overcome these issues, we have re-designed the test program structure and developed a standard architecture and framework for all test programs in Numonyx. This architecture allows us to develop a Generic Test Program (GTP) that will be shared for all products of the same family. The architecture allows for full separation between the high level realization of test (generic C code or any other tester language) and the low level realization of testing platform functions. This platform independent design enables much faster test program conversions to different testing platforms. The framework developed provides a set of shared functionalities that are reused by all products and platforms. All tests are developed in such a way that the high level code describes the nature of the test, while a post processor runs on the test and complies the test with the product definition files that are completely external to the test program definition, and with the testing platform definitions, producing a final compiled and optimized code for the given platform.Using this approach has shown to reduce up to 50% of the test program development time and up to 90% of the conversion time between platforms.

Biography

SESSION 4: Achievements of Focused Companies

Automated Failure Analysis Flow on BIST supported Memory Devices

Abstract

Semiconductor manufacturers need to insert the testing operation in the manufacturing flow, due to the inability to produce ‘perfect’ devices. Beyond screening of defects, which is the principal task of the testing, it is essential to understand the reason of the malfunction and trace it back to the critical process step, to allow the correction and the yield improvement.
The understanding of the root cause of the defect might be rather complex and often requires human recognition operations. Summary test results (binning), used for statistical yield analysis, hide the necessary details. Standard test data logs highlight the failing evidence (like the result of the pattern matching): this datalog might contain all necessary information, however the process to reach the origin of the failure is rather challenging.
This process is particularly critical for BIST enabled memory devices, due to the fact that the data output of the BIST engine has to be transformed into the failure mechanism of the memory cell or array. The manual computation is not practicable, nor the on-line data analysis due to test time constraints. Our paper is going to present a fully automated test data analysis flow, including test data collection, fail signature extraction and statistical processing. The test data logs, divided in a standard format (STDF) and in a custom (XML and S-Record based), memory related extended information, are imported by a data collection system. The applied technology allows the optimized storage and access of the large amount of data.
Once the full data is available, a dedicated post-processing procedure is triggered. The output of the BIST data engine is processed, combining it with the description of the device and with the description of the BIST test. The aim is twofold: the topologic fault classification at array level (single bit, wordline, bitline, cluster, …) and the identification of the failing mechanism at cell level (stuck-at failure, coupling failure, …). The results of this procedure might be input of further statistical and correlation analysis tasks.
The software environment, which allows the execution of this procedure in a fully automated manner, will be discussed. Screenshots will be shown about the system configuration operations like the definition of the device topology and scrambling the BIST operations. The presentation of the fail information at device (array) level as well as wafer level will be shown. Statistical wafer maps (identification of fail signatures, stacked maps) will be displayed as well. We are going to show also the trace-back of this information to physical, transistor level, for driving Physical Failure Analysis (PFA).

Biography

IC Yield, Reliability and Prognostics Using Nanoscale Test Structures

Abstract

The mounting issues of decreased yield and reliability from nanoscale IC processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes. Nanoscale transistor sizes and related semiconductor reliability issues (also affecting manufacturing yield) are emerging as a major concern to the long term reliability of safety‐critical systems in aerospace and automotive applications.
Common semiconductor failure modes that also contribute to end‐of‐life failures include Time Dependent Dielectric Breakdown (TDDB), hot carrier damage (HCI), Negative Bias Temperature Instability (NBTI) and metal migration. All of these common failure modes are far worse at nanoscale geometries. Fortunately there are methods tat counteract these common failure modes. Die‐level prognostic test structures can detect and help mitigate the untimely failures in critical systems. These test structures, with variance measurement capabilities, also provide an effective platform for improved process‐aware design for improved yields. Electronic prognostics, uses measurement observations to develop predictions of impending failures in an observed system, yielding an “early warning” of a pending system failure so that appropriate corrective actions can be taken prior to the occurrence of the effective failure of the system. In addition the electronic prognostic measurement data also provides information to properly determine the remaining useful lifetime of a circuit or system as well. This presentation will address concepts of electronic prognostics, also known as predictive diagnosis, through use of in‐situ test structures as a solution to yield, reliability and prognostic applications and includes practical application examples. Electronic prognostics, uses measurement observations to develop predictions of impending failures in an observed system, yielding an “early warning” of a pending system failure so that appropriate corrective actions can be taken prior to the occurrence of the effective failure of the system. In addition the electronic prognostic measurement data also provides information to properly determine the remaining useful lifetime of a circuit or system as well. There is a well‐known, and on‐going push to smaller IC process geometries. These smaller processes increase the density of circuitry on the silicon, and have helped in implementing increasing higher levels of functionality in ICs (“From the law of Moore to More than Moore”).
However, there has been growing evidence that these transistors are introducing reduced lifetimes and wider process spreads. For critical applications intended for long service lives, (aerospace, medical, automotive), this is a growing problem.
At a basic level, IC design assumptions are that the transistors are identical and design methods leverage matched pairs to cancel drifts and offsets. When there is mismatch within pairs occurring, this introduces errors that affect yield and long‐term life of the ICs. In addition to mismatch, other effects are affecting long‐term performance, including gate oxide wear‐out through time dependent dielectric breakdown (TDDB) of the gate oxide, hot carrier damage effects, and negative bias temperature instability (NBTI). These effects have the effect of reducing production yields, reducing important performance margins, and reducing the long‐term life of the IC. Threshold voltage shifts, for example, can cause timing errors in digital circuits, or gain errors in analog circuits. In order to manage these effects, a method of observing what is occurring at the silicon level is important. This rests on the foundation premise that a process cannot be controlled, unless it can be observed. The observation is provided through the creation of unobtrusive, precision test structures that measure these parameters and allow the user to mitigate their effects. In the area of mismatch, the parametric variation of ΔVT, ΔI(on), ΔR and ΔC across a die can be very large and cause yieldlosses. However, the measurement can also be used to adaptively correct for their impact on the circuit performance. This closed‐loop correction process can provide “process‐aware” design capabilities that improve production yields. For post‐fab analysis, these buffered test structures also overcome the potential damage from physical probing.
On the impact of test structures TDDB and HCI, the detection of these phenomena can be supported through the adoption of “canary” type test structures that notify when a pre‐set threshold has been exceeded. Since both TDDB and HCI scale by voltage and area, the canary thresholds can be adjusted through adjustment of the physical structure’s size and voltage. Upon triggering, a transition to a backup IC can be made to assure uninterrupted operation.
NBTI is a transient effect that causes a threshold voltage shift from temperature changes. Upon reduction of temperature, the shift relaxes and normal operation can resume in the circuit. However, this can cause troublesome intermittency faults that are difficult to isolate and repair. For example a pilot in an aircraft can report a problem with the flight control computer, but when the unit is removed for service, the diagnostics do not find the fault. This intermittency fault from NBTI can be detected and provide the service personnel with valuable information in repairing the problem.
Prognostics, or predictive diagnostics, can be valuable in supporting advanced condition‐based maintenance (CBM) strategies. Physical wear can vary considerably from system to system, and CBM allows the precise adjustment of maintenance intervals based on usage and wear, rather than equalinterval that are costly and of limited effectiveness. In complex electronic systems, prognostics requires consideration of faults beyond the die‐level and can occur at five different levels; die, package, board, module, and system. These additional levels will also be discussed, along with considerations to the extraction of wear‐out signatures, their analysis and linkages with other systems and practical examples of prognostic applications.

Biography

Panel Discussion: “Can we make our business more efficient by focusing, outsourcing and sharing key resources?”

Panel introductory presentation: Labless Model Accelerated Adoption In Europe

Abstract

The semiconductor industry continues to go through major transformations, even as we pass the 60th anniversary of the invention of the transistor. After fantastic market growth through manufacturing innovation, came the emergence of the foundry and fabless model, followed by the disintegration of the traditional, “do-it-all” Integrated Device Manufacturer (IDM) framework. New shifts are now taking place in the engineering space; with its emphasis on “More than Moore” designs, Europe is a fertile ground for spearheading such new models.
The travails entailed by the painful transition through 130nm (copper) and 90nm (lithography) shifted our industry powerbase from “the CTO to the CFO”. New business models called for focusing on core competencies that best leverage investment in technology, and somewhat limited its scope. This in turn accelerated outsourcing of functions that could be pooled together for efficiency of scales outside of IDM: assembly and test (massively); wafer fabrication (selectively); design verification and physical layout. 
Product engineering has traditionally been considered both core, and difficult to outsource. This remains true today; however, new collaborative frameworks permit a balancing of the need for proximity with the necessity for cost efficiency. A new model called ‘labless’ implements a web of independent “Hubs” that group, around key test (ATE) capabilities, the means necessary to execute product engineering cycles (test, qualification, reliability, and failure analysis). This model enables semiconductor companies to lower cost, to gain in efficiency and to continue to pursue aggressive technology roadmaps, while preserving the integrated infrastructure required by designers and product engineers. This model has been successfully used by some pioneering companies and is now on the verge of been largely adopted by the industry. With increasing investment costs in domains like RF or 3-D integration, this adoption will be accelerated. 
One school of thought today in the financial community advocates the notion of “No More Moore” in order to reign in new process investment; here in Europe, we are pushing for “More than Moore”, which looks at increasing the value content of microelectronics by integrating heterogeneous elements. This trend brings silicon much closer to end-user applications; it drives designers to think “system” instead of “component”. It will force companies to continue streamlining organizations and be even more selective in the selection of what will remain core for business success. Successful companies will be those able to evaluate, to qualify and to deploy integrated supply chains that incorporate external units in tightly-knit system-level product design flows. The labless model will be an integral part of this strategy, and will flourish in Europe.

Biography