Advanced Packaging Conference

The Power of Packaging

Date: 8 - 9 October, 2013

Time: 13:00 - 17:30 / 09:00 - 13:00

Location: Ballroom, Messe Dresden

 

The Advanced Packaging Conference provides a unique opportunity to learn more about new developments, package technologies, applications and package solutions for various products used in power applications and system integration. 
New Advanced Packaging technologies and processes for Power Electronics, LEDs, MEMS and Embedded devices are being initiated by European companies together with international OEMs, IDMs and Fabless organisations. Many challenges need to be addressed, in order to package new devices at low cost. For System Integration, the package is now an integral part of the system functionality, be it System-in-Package, More-than-Moore or Heterogeneous Integration at wafer level and on organic substrates. R&D and manufacturing here in Europe are providing the leading Packaging solutions.
The presentations will include Keynote papers from ASE and from Qualcomm. The conference will cover aspects of Power Handling, Size, Interconnection Interfaces, Thermal Management and Heat Dissipation. The programme will shed light on recent application specific packaging technologies, processing and manufacturing related technologies which can be leveraged as key enablers for cost efficient electronic devices and systems.

 

 

 

Sponsored by:

 

EVG, Logo

 

 

SPIL, Logo

 

 

 
Media Partner:

 

 

 

AGENDA

 Tuesday, 8 October

  

Session 1:

Applications & Processes

Chairman:Steffen Kröhnert, Director of Technology, NANIUM
 
13:00Introduction
Yann Guillou, Business Development & EU Standard Manager, SEMI Europe
 
13:10Keynote:
Smart SiPs to Propel Smart Living
Ho-Ming Tong, General Manager & Chief R&D OfficerAdvanced Semiconductor Engineering, ASE Group
 

13:45

 

Countering counterfeits of electronic components by insertion of Anti-Counterfeit Technologies into IC packages

Stephanie Pesseguier, Technical Product Security Manager, STMicroelectronics

Bruno Laguitton, Head of the anti-counterfeiting activities, CEA-Leti

 

14:10

 

Compression Molding: solutions for 3D TSV and other advanced packages as well as cost savings for standard package applications
Huub Claassen, Managing Director, Towa Europe GmbH
 
14:35LowTemp(TM) Room-Temperature Debonding: Lifting processing restrictions
Thomas Uhrmann, Business Development Manager, EV Group
 
15:00Coffee Break
  

Session 2:

Power Packaging

Chairman:Klaus Pressel, Infineon
 
15:35Power electronics packaging: industry shifts gear
Christophe Fitamant, Sales & Marketing Manager, Yole Développement
 
16:00High-performance power-module for hybrid- and electric vehicles
Eckart Geinitz, Project Manager, Robert Bosch
 
16:25Delamination Failure Modeling for PowerPackages and Modules
Rainer Dudek, Project leader, Fraunhofer ENAS, Micro Materials Center
 

16:50

 

Evaluation of Pressureless Silver Sintered High Power Semiconductor Devices by Measurement of thermal Impedance
Martin Beierlein, Student, Hochschule Aschaffenburg
 
17:15Networking Reception
 
 

 Wednesday, 9 October

   

Session 3:

Wafer Level Packaging

Chairman:Jens Mueller, Head of department: Electronics Technology, TU Ilmenau
 
09:00Introduction
Jens Mueller, Head of department: Electronics Technology, TU Ilmenau
 
09:10Keynote:
Mobile Device Challenges Leading Packaging Innovation
Steve Bezuk, Senior Director, Engineering, Advanced Packaging, Qualcomm
  
09:45Drivers for Advanced Packaging:  Thin is In!
Jan Vardaman, President, TechSearch
  

10:10

 

More Package, Less Board - System Integration on Component and Board Level for More Performance on Less Space
Steffen Kröhnert, Director of Technology, NANIUM
  
10:35HVM Bump and Cu Pillar quality control in a highly dynamic foundry environment
Alexander Platz, Manager Bump Process Integration, GLOBALFOUNDRIES
 
11:00Coffee Break
 

Session 4:

3D Packaging

Chairman:Rolf Aschenbrenner, Head of Chip Interconnection Technologies, Fraunhofer IZM
   

11:35

 

Alternative Package-on-Package with Routable Substrate Interposer for Stacking Solution
Steven Lin, Senior Technical Manager of Customer Advanced Product Div, SPIL (Siliconware Precision Industries)
 
12:00Strength of Thin Glass Foils for Electronics Encapsulation
Kurt Nattermann, Principle Scientist, Schott AG
  
12:25Assembly and Interconnect Technologies for 3D Applications
 Juergen Grafe, Section Manager, Fraunhofer IZM
  
13:00Closing Remarks
Jens Mueller, Head of department: Electronics Technology, TU Ilmenau
  
  

Who should attend?

The conference will review the Technologies, Materials, Processes and Equipment that are being developed in Europe and elsewhere, to spearhead the take up of these advanced packaging needs. Attendance at this exciting conference should be a high on the list of priorities for anyone involved in the needs of future device packaging, including design, development and production. SEMI welcomes the interest of managers, engineers and technicians from the whole spectrum of the semiconductor industry.

 

Price* Information and Registration

 
 Before 30. SeptemberAfter 01. OctoberOnsite
SEMI Members315.-365.-415.-
Non-Members365.-415.-415.-
* all Price information in EUR, VAT not included

 

Organizing Committee:

• Rolf Aschenbrenner, Fraunhofer IZM

• Eef Bagerman, NXP

• Eric Beyne, IMEC

• Andreas Fischer, Bosch

• Michel Garnier, STMicroelectronics

• Albert Koller, Oerlikon

• Steffen Kröhnert (co-chair), NANIUM

• Andy Longford (co-chair), PandA Europe

• Jens Mueller, IMAPS Europe Chapter

• Thomas Oppert, Pac Tech

• Amandine Pizzagalli, Yole

• Klaus Pressel, Infineon

• Klaus Schrimper, Hesse-Knipps