About the presentations:

III-V and III-V on Si for future nanoelectronics

Abstract:

In order to continue transistor scaling while improving device performance, new materials have been introduced into Si CMOS transistor technologies. Some examples of new materials recently implemented in Si CMOS processing are embedded SiGe strained Si, high K gate dielectrics, and metal gates. III-V materials are currently being researched as an alternative transistor channel material because of greatly increased electron mobility compared to Si. In this paper, the performance of scaled III-V field effect transistors is benchmarked compared to those of Si FETs, and advantages are demonstrated. Challenges for the implementation of III-V in a Si CMOS technology node are outlined. Solutions for some of the challenges are shown, such as integration of III-V onto Si substrates and the development of a high quality gate dielectric interface on the III-V channel material. A high mobility pMOS material is necessary for a CMOS technology and work is shown on strained InSb transistors. Despite the challenges, significant progress is being made and III-V materials remain a promising option to continue to enhance transistor performance and enable future high performance and low power logic applications.

In Situ Control of ALD Processing

Abstract:

Atomic Layer Deposition has established itself as one of the key processing technologies in the sub 70 nm nodes. The possibility to grow materials by chemical vacuum deposition in a self limiting fashion on a sub monolayer scale, enables precise control of well defined materials even in hided surface topologies with extreme aspect ratios. The simple concept of ALD as a cyclic repetition of alternating precursor and carrier gas steps tempts to believe that the growth process is inherently stable. However especially in the initial phase of first closed layer formation it turns out that control indicators are mandatory. We will show results of in-situ monitoring by using Quartz Microbalance (QCM), Mass Spectroscopy (QMS), Spectroscopic Ellipsometry (SE) as well as in line monitoring without vacuum break, applying Scanning Microscopy (AFM/STM) and Photoelectron Spectroscopy (XPS). Besides fundamental results on the growth initializations, relatively simple monitoring concepts well suited for manufacturing processing control are presented.

A combined Etch, Cleaning and k-restore Process for less damage integration of ultra low-k materials.

Abstract

This paper describes a complete patterning regime for the integration of dense and porous SiCOH low-k films in 45 nm node copper/low-k damascene technologies. It could be shown, that the exact coordination of etch, post etch clean and k-value restore processes with the timeline of Figure 1, bears a high importance to integrate the sensitive low-k materials without a serious destruction.
During the etch process, the SiCOH materials will be damaged with the result of an undesirable increase in their dielectric constants. The different mechanisms, which occur during such processes, are shown in Figure. 2. The capability of selected additives to minimize the low-k sidewall damage during reactive ion etching (RIE) of SiCOH material in fluorocarbon plasmas was discussed in several works in the past. Most of the investigated additive gases alter the fluorine to carbon ratio as well as the dissociation of the parent gas inside the etch plasma [1]. The result is a changed etch rate, an modified polymerization behavior and other characteristics of the process induced SiCOH damage. In this paper the additives Ar, O2, C4F8, H2, N2 and CO were added to a conventional CF4 etch plasma, to provoke different changes in the plasma conditions and therewith in the process results, see Figure 3. With respect to our investigations the additive gases N2 and H2 are the best approaches to improve etch processes for SiCOH materials in fluorocarbon plasmas.
By using the method of Owens, Wendt, Rabel and Kaelble (OWRK) the energetic character of a porous low-k material after a CF4 etching process with several additives has been determined.
Usually the polar and dispersive surface energy contributions are calculated to evaluate the wetting behavior of this surface by certain wet cleaning solutions [2]. Additionally this method turned out to be useful to determine the surface conditions altered by different etch treatments and can be used to evaluate whether the surface near areas of the dielectric are damaged by those plasma processes or a polymeric layer has been deposited. In pristine condition the porous low-k material turned out to be nearly completely dispersive with a rather low surface energy of less than 30 mN/m. The etching processes lead to the introduction of a polar surface energy contribution strongly depending on the additive used, see Figure 4. With respect to these results the increased significance of the etch chemistry on the following post etch clean is demonstrated.
Finally a k-value repair process based on a silylation reaction was developed. In this case, polar – OH groups are being removed and substituted by non-polar carbon containing species. Chemicals like Hexamethyledisilazane (HMDS), Octamethylecyclotetrasiloxane (OMCTS) and Tetramethylecyclotetrasiloxane (TMCTS) applicated in wetchemical or gas phase based regimes are promising candidate to recover the ULK’s material properties. This reaction can be advanced by thermal treatments, as well as UV radiation, which can promote desorption of water and OHspecies that leads to increase the free bonding places for silylation reagents. In our experimental studies it could be shown that UV treatments with wavelengths of 172 and 185 nm caused a higher damage with shrinking of the films. In case of 222, 254 and 283 nm positive repair effects were achieved, see Figure 5.
This work describes a possible way to reduce the destruction of low-k materials during their patterning. Not only the improvement of single process steps but also a complete regime with concerted processes is necessary to overcome damage problems in the framework of opper/low-k integration.

Epitaxial Process Technology for SiC

Abstract

Silicon carbide(SiC) is now attracting attention as the devices for energy saving and the prevention of global warming. SiC is much superior than Silicon in terms of wider band gap, higher breakdown field and thermal conductivity, and SiC devices provide new opportunity for high voltage, fast switching and high temp applications. However, one limitation of growing SiC market is the difficulty of its epitaxial process. We have developed new SiC epitaxial growth process tool with sophisticated process and productivity and brought technological innovation to SiC market.