Lithography Session Date: 21 October, Messe Dresden Room: TechARENA, Hall 1 (free for all visitors)

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Sessions on the SEMI TechARENA are free and do not require pre-registration. Seating is limited, please arrive early.
Session chair: Wolfgang Arden, Infineon and Mark Staples, GLOBALFOUNDRIES
10:05	SEMI overview and Standards Update
10.15	“Lithography Challenges in Advanced Logic Semiconductor Manufacturing” Rolf Seltmann, Lithography ,GLOBALFOUNDRIES
10.35	“22nm CMOS Lithography Patterning UTTERMOST Project” Dominic Goubier, STMicroelectronics
10.55	“Methods and Challenges to Extend Existing Dry 193nm Medium NA Lithography Beyond 90nm” Jens Schneider, Principal Lithography, Infineon Technologies Dresden
11.15	“A Practical Approach for Inverse Lithography Technology Application” Chin Teong Lim, OPC/RET Coordinator, Infineon Technologies Dresden
11.35	“EUV Lithography: Recent Achievements of a Maturing Technology” Roel Gronheid, Senior Scientist, IMEC
11.55	“Multi Shaped Electron-Beam Technology for Mask Writing Application” Speaker to be determined, Vistec
12.15	“Photolithography Enhancement by Source Mask Optimization in Mask Aligner Lithography Systems” Michael Hornung, Project Manager Application Development, Suss

About the presentations:

Lithography Challenges in Advanced Logic Semiconductor Manufacturing

Abstract

Traditionally, the ITRS always was driven by memory applications, both with respect to resolution and overlay requirements. Logic primarily focused on transistor performance, maintaining excellent leakage and corresponding across chip line-width control (ACLV). Within our talk, we will discuss different methods to improve ACLV and the electrical performance of state of the art microprocessors. Going from the 180nm node down toward the 65nm logic node, the corresponding critical dimension shrink was always supported by new innovations on the tooling side (wavelength, NA), thus keeping the k1 in the comfortable >0.4 range. This road seemed to come to an end when 157nm lithography was dropped off the roadmap. However, due to the success of immersion lithography, k1 could be kept in the 0.4 range even at the 45nm node. AMD (GLOBALFOUNDRIES) was the first company in the logic area that consequently stepped into immersion and introduced it into volume production way ahead of anybody else outside the memory business. We will discuss several challenges related to the introduction of immersion and show how we solved it. With the introduction of the 32nm and the closely following 28nm and 22nm nodes, no major push from the tooling side can be expected anymore. As EUV is pushed out toward post 2012, both NA and wavelength will stay at 1.35 and 193nm, respectively, and logic lithography quickly goes down the way to k1<0.3, coming close to the theoretical resolution limit. To avoid costly and cumbersome pitch splitting techniques, the only way to survive lies in a better control of lithography. In the pre-production phase, it becomes of paramount importance to make designs more lithography friendly (DFM). This includes pitch limitations, layout decomposition techniques into two individual masks and eventually a joint optimization of the illumination source of the scanner and the optical proximity correction (OPC) of the layout on a mask, known as “Source Mask optimization” (SMO). Several examples will be touched within our talk. The other branch of innovation belongs to the production phase. Perfect tool and process control becomes essential. The following innovations will be subject of the talk:
- New focus closed loops to address design, process, scanner chuck and lens impacts on defocus
- New methods to reduce remaining OPC imperfections, in particular those that are related to exposure tool differences
- Methods to tighten the CD distribution both at the mask and the wafer.
Besides imaging, perfect overlay control at logic becomes important as well. We will show methods that are aimed to tighten the overlay variation both at the mask and the wafer. We will introduce innovative sampling techniques that allow the compensation of both the lens, reticle and wafer signatures.
Finally, we will take a view into the post 22nm nodes, in particular from a foundry point of view. We will discuss the pros and cons of EUV versus Immersion double patterning techniques.

Biography

Rolf Seltmann, Lithography , GLOBALFOUNDRIES Rolf Seltmann got his Diploma in Physics from Dresden University in 1975. After working in applied optics for several years, he joint ZMD Dresden in 1983 as an R&D engineer. From 1983 to 1990 he worked in the field of ion beam projection lithography and photolithography, respectively. In 1990, Rolf joined the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Dresden where he acted as project manager for the development of a new, SLM-based Laser Pattern Generator. Since 1997 Rolf is with Advanced Micro Devices (AMD) Fab30/Fab36 and its successor GLOBALFOUNDRIES Fab1. There, Rolf was in charge for the introduction of Step&Scan systems of 248nm and 193nm wavelength, including immersion, into GLOBALFOUNDRIES’s Fab’s. Furthermore, he worked on the characterization and reduction of the impact of process variations (CD, overlay) on the performance of state of the art microprocessors. Being an AMD and GF Fellow since 2005, he currently is in charge for development activities within Lithography in Fab1 and acts as a member of the Technical Advisory Board of the Advanced Mask Technology Center (AMTC) in Dresden

Methods and Challenges to extend existing dry 193nm medium NA lithography beyond 90nm

Abstract:

In order to fulfill the demands of further shrinkage of our mature 90nm logic litho technologies under the constraints of costs and available toolsets in a 200mm fab environment, a project called "Push to the Limits" was started. The aim ís to extend the lifetime and capabilities of existing dry 193nm litho toolsets with medium to low numerical aperture, coupled with the availability of materials and processes which were known to help up CD miniaturization and to shrink the 90nm logic litho process as far as possible. To achieve this, various options were explored and evaluated, e.g. optimization of illumination conditions, evaluation of new materials, usage of advanced RET techniques (OPC, LfD, DfM and ILT) and resolution enhancement by chemical shrink (RELACS). In this project we demonstrate how we were able to extend our existing 90nm technology capability, down close to 65nm node litho requirements on most critical layers. We present overall result in most critical layer generally and specifically on most difficult layer of contact. Typical contact litho target at 100nm region was enabled, while realization of 90nm ADI target is possible with addition of new process materials

Biography

Jens Schneider, Principal Lithography, Infineon Technologies Dr. Jens Schneider joined in 1985 the University of Giessen in Applied Physics. In 1995 he achieved a PhD in the field of high temperature superconductive flux-flow devices. Since 1991 he worked as a scientific staff member at the Institute of thin film and ion technology at the Research Center in Jülich. In collaboration with Siemens he was responsible for the deposition of large area high temperature superconducting thick films for resistive current limiter applications in power plants. In 1998 he joined the semiconductor business with Infineon in Munich and is currently the Lithography Principal of Infineon Dresden

A Practical Approach for Inverse Lithography Technology Application.

Abstract

Among a number of available OPC solutions ILT provides the best process window, its application to a full chip is however problematic. Typical mask pattern outcome of ILT is represented by smooth shapes and has to be further simplified or pixelized in order to improve mask writing time. As a mask is becoming another optical element and a pattern doesn't look like original design, arial image mask inspection has to be adapted in order to cope with mask defects characterization. A degree of ILT pattern simplification depends on a trade-off between reticle manufacturability and overall process window combined with careful control of SRAF printability and possible hot spots.
Lithographers are continuously searching for a full chip solution that provides manufacturable mask shapes and acceptable runtimes. With a goal to establish the best ILT practice, our idea of applying ILT selectively to the areas of a chip where it's needed the most has been verified on a 65nm gate contact layout using low NA 90nm node tools. Selective or partial ILT was found to be a bridge for the transition towards eventually full-chip ILT due to higher mask writing time, inspection and resultant mask CD non-uniformity.
We suggested combining different simplification schemes to address process window for different pitch ranges. We have scanned a typical C65 contact chip logic layout excluding dense SRAM and considered only projecting CH (projection length exceeding 45nm) to find out the counts of various pitch' occurrences. Dense pitch range had the highest count and if dense pitch range can be resolved with direct OPC and special illumination choice then approximately 30% of remaining pitches would require inverse OPC treatment as they belong to forbidden pitch range.
Complete ILT treatment of a chip would lead to unreasonably high mask writing time. Typical pattern simplification such as minimal polygon area restriction would lead to slightly shorter mask writing time. However by selectively applying ILT treatment, only a fraction of a chip would require longer mask writing time. We will further explore pitch-based selection criteria, and investigate this hybrid OPC flow in more detail. Additionally we discuss furher improvement of run-time and mask complexity based on new emerging RET technique and how to reduce the technical complexity of current ILT approach.

Biography

Chin Teong Lim, OPC/RET Coordinator, Infineon Technologies Studied physics and obtained BSc in Physics from University of Malaya in Kuala Lumpur, Malaysia, 1996. Prior to joining Infineon Dresden in April 2005, he worked for Seagate in Lithography Department (1996 April - 1999 Aug) and Silterra on both lithography process & OPC development (Sep 1999 - Mar 2005). Today he is leading RET (Resolution Enhancement Techniques) & OPC (Optical Proximity Correction) at Infineon Dresden

EUV Lithography: Recent Achievements of a Maturing Technology

Abstract

The implementation of EUV lithography for pilot-production is rapidly approaching with the first full field pre-production systems being shipped in 2010. In preparation for this, the EUV ADT at imec is being used to identify and improve the critical technological challenges for implementation of this technology. In this contribution an overview of recent accomplishments in system performance and mask defect printability will be given. In more detail the challenges and recent improvements on EUV resist materials will be discussed.

Biography

Roel Gronheid, Senior Scientist, IMEC In 2001, Roel Gronheid received his Ph.D. in Photochemistry from Leiden University (the Netherlands) and had a post-doctoral position at the Catholic University of Leuven afterwards. He joined IMEC in 2003, where he specializes in advanced resist technologies within the lithography department. He has been actively involved in IMEC’s 157nm, 193nm immersion and EUV lithography research programs and has autored and co-authored over 60 publications and technical conference presentations. He currently manages the work on resist fundamentals in IMEC’s lithography affiliation program

Photolithography Enhancement by Source Mask Optimization in Mask Aligner Lithography Systems

Abstract
Since the very beginning of semiconductor industry in the early 60s, proximity and contact lithography systems, so-called mask aligner, were the workhorse of their success. The never ending rush for higher resolution had pushed mask aligners out of front-end lithography many years ago. However, innovation and constant improvement of mask aligners have always opened new applications and markets for cost-effective optical lithography. Today, mask aligners are widely used in research and development, in micro-fabrication, in Advanced Packaging, MEMS and LED manufacturing, for thick photo resist applications, and most recently also for (Nano) Imprint Lithography, Wafer-Level Camera and Watch Making. However, the improvement of the illumination systems of mask aligners was widely neglected. A standard illumination system of mask aligners use a multipole off-axis illumination to reduce diffraction effects (side-lobes), as shown in Figure 1 only.
The novel illumination system for mask aligners provide improved exposure light uniformity and customized illumination (Figure 2). The illumination system, the so-called MO Exposure Optics, is based on two consecutive Köhler Integrators and an exchangeable illumination filter plate. The double Köhler Integrator concept allows homogenizing of both irradiance and the angular spectrum of the exposure light over the full mask area. The exchangeable illumination filter plate allows a free choice of illumination settings, like e.g. ring-illumination, quadrupole, multipole, Maltese cross and free-forms in a standard mask aligner. The MO Exposure Optics significantly improves the depth of focus (DOF) and exposure latitude while reducing mask error factors for full-field proximity lithography in mask aligners. The MO Exposure Optics now allows a free choice of illumination to adapt diffraction reduction to the actual mask pattern, resist type and proximity gap.
This opens the filed of source mask optimization which is a Photolithography Enhancement Technique commonly used in Projection Lithography to compensate for image errors due to aberrations, diffraction or process effects. Source mask optimization is now available for Mask Aligner Lithography. This novel concept allows to precisely shape the illumination light and mask pattern to correct aerial image and process errors in both contact and proximity lithography beyond today’s limits, e.g. compensation of print errors like corner rounding and line edge shortening on mask using optical proximity correction (OPC) (Figure 3). This customized illumination and OPC-like structures introduce well-know tools of projection lithography for mask aligners for the first time.

Biography

Michael Hornung, Project Manager Application Development, Suss Michael Hornung is project manager at Suss MicroTec Lithography based in Garching, Germany. He is responsible for the (nano) imprint technology team. Together with his team Dr. Hornung developed several new imprint toolings for Suss mask aligners. Before taking over this job he leads the application group responsible for the whole lithography processes on mask aligner, coater, bonder etc. Before he joined Suss MivroTec he was project manager at CERN in Geneva, Switzerland, working at the inner detector for the ATLAS project. Michael Hornung holds a Ph.D. degree in Natural Science from the University of Freiburg. Germany